basic question about biasing

[airboss]

Hi,

I have a fundamental question about biasing. I'm sizing the fets on cascode. I know I'm supposed to do current biasing but I still have some questions....
Suppose MN is an NMOS at the bottom of a cascode and Mb is its biasing current mirror, which is a diode-connected transistor. MN_G is connected to Mb_G.
After the allocation of current and Vov, I can start to size MN and Mb. I'm thinking that, since they have the same source voltage( both connected to gnd) and the same gate voltage. They're using the same length. Theoretically, if they have the same width, they'd have the same id. So I sweep the width of Mb and find the width that can give me the Vov I want. However, when I set W_Mb = W_MN, I always get id_MN<id_Mb.
On the other hand, if I size w to get the same id of both transistors, Vov is usually much different from the Vov I allocate to the transistor.
Can anybody point out the mistake I make and tell me what the correct way is?

Thanks in advance.

 

[paulux]

The mismatch is due to early effect of the transistor Mn. This can be improved with longer L.

 

[pfd001]

Id is not only dependant on the W/L, also dependant on the Vds

 

[gte582w]

using long L or cascode it will reduce this mismatch.

 

[heartwide]

It is called channel-length Modulatioon Effect, dependented on L of device, and have a factor
named lambda which having value of (0.005~0.03) in general.