Bandwidth requirement of op-amp for ADC

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shanmei

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If the resolution is N bit, sampling frequency is Fs, feedback factor is beta, how can we get the bandwith requirement? Thanks.
 

Hi,

In detail it depends on stability, too. It means: how long it takes for the output to settle.
Some ADC (indeed the S/H circuit) couses some glitches at the ADC input ... and thist causes ringing in the Opamp circuit.
The ringing needs to be stopped until the ADC starts a conversion.

But as a rule of thumb I've heared: max signal bandwidth divided by the expected error.

Example:
if signal bandwidth is 10.000 kHz and the expexted error should be less than 1% (=0.01l)
then: bw >= 10.000kHz / 0.01 = 1MHz

Klaus
 
Thank you for your reply.

From the paper: "An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit", it mentioned that if the sampling rate is Fs, N-bit resolution, and the feedback factor is beta, then the unit gain bandwidth of the S/H amplifier should be larger than 2(N+1)*Fs*ln2/beta.

Comparing it with your equation "signal BW/error". Assume N=7( error 0.01), beta=0.5, and Fs=2*signal BW=20K, then the result 2(N+1)*Fs*ln2/beta=3MHz, which is quite close to your result. So the equation of "signal BW/error" is very handy.

I just don't know how they get the equation 2(N+1)*Fs*ln2/beta.
 

Check the attached image.
The reason why there is (N+1) rather than N is because the accuracy required was less than half the LSB.
 
Thanks, vivekroy.

I found that if the input signal is 50MHz, and the resolution is 10-bit(0.001 error), according to the equation of "signal BW/error"=50MHz/0.001=50GHz. 50GHz is much larger than the required bandwidth.

The equation of 2(N+1)*Fs*ln2/beta=2*11*50M*0.7/0.5=1.54GHz is more accurate.
 

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