Bandgaps output value changes from chip to chip!

[tia_design]

About Bandgap

I designed a CMOS bandgap, in which there is an op amp. When I measured the bandgap's output, I found this value changes from chip to chip. So what could be the reason causing this change. Thanks!

 

[leo_o2]

About Bandgap

How much variation? if within+/-5%, it is reasonable.
It is according to process variation.

 

[iamxo]

Re: About Bandgap

It is ofcourse different, due to process variation.

I will not believe that it is all the same between chips.

 

[slchen]

Re: About Bandgap

The bonding and package also make the output voltage variation (several volts).

Sorry!! it should be several mV.
Thanks!! Leo_o2

 

[leo_o2]

About Bandgap

Hi slchen,

Several volts? many ten of mV for package shift.

 

[manissri]

Re: About Bandgap

variation wud me 10 of mv

 

[tia_design]

Re: About Bandgap

Thanks a lot for your guys reply. I appreciate that.

 

[kobeghost]

About Bandgap

several mvs,Is there any possibility of changing so much between the chips.If that case occurs,should we take the design problem into consideration

 

[bicave]

About Bandgap

you can use TRIM method for more accurate

 

[she_long]

Re: About Bandgap

I think the variation comes from process variation, not from the bonding and package. The trimming is for the die not package.

 

[pfd001]

About Bandgap

it is reasonable to change seveal mvs.

 

[finalvolition]

About Bandgap

It depend on fab process and your design.
Basically, using larger device size can avoid variation due to Vt .

 

[chaojixin]

Re: About Bandgap

The bonding and package also make the output voltage variation (several volts).

Sorry!! it should be several mV.
Thanks!! Leo_o2

how can bonding and package affect the output? i my opinion, the bonding wire contains only ind and cap which wouldn't affect DC point. is it something to do with stress? or other factor?

 

[dick_freebird]

There are strain effects from packaging, piezoresistive; I've seen some people lay out
their bandgap resistors at 45 degrees because it gave them a little bit less. Seemed
like overkill to me but they swore by it.

Are you really expecting your CMOS op amp to have less than 10mV random Vio
scatter? Good luck with that.

 

[keith1200rs]

This thread is 4 years old!

Keith