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bandgap start up too slow

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dawn goh

Newbie level 5
Sep 29, 2009
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hi, can i ask a question here. i am new to bandgap design and have design a very simple brokaw cell without any opamp sensing circuit for feedback. i am facing a problem with a slow start up circuit, i am support to start up the circuit after 500ms but right now its 1s. The start up i use composes of a resistor and a few diode drops connected to the gate of a npn whose emiiter will drive the base of an npn. Anyone can give me some hints? Thank you very much.

I think the current through start-up circuits should be increased so the capacitor at base of a npn will be charged faster.

Added after 1 minutes:

Try to decrease resistor in a start-up.

hi... i tried increase/decrease current, change diode sizes, still no changes :cry:
can someone give me some ideas?? thanks in advance

The problem is that the capacitance at the output is charged too slowly, with other words the desired current is not present. If you burn lot of current, than they flow probably somewhere else.
A drawing of the circuit would be useful, for more help.

hi, here are 2 separate files attached
the first is the start up circuit, sorry, i drew it using word, could not print screen it at the moment sth wrong with my comp
the 2nd one is the ieee paper - a simple 3 terminal IC bandgap reference by brokaw. I am using fig 4. the emiiter of the nmos is connected to Q1 while Q10 and Q11 are implemented with cascode, vdd 4V

Its self biasing and has no other input except for the Vdd which is ramped from 0s to 1s to 4V. Base of Q2 is the output of the intrinsic bandgap voltage 1.4V while R4 and R5 is to step up the voltage to 2V, which is the specs. This 2V takes about 1s to reach this value. The current in the main branches of Q5 and Q6 are each about 12uA. The start up circuit compose of Qs, R5 and the string of diodes.

can anyone help me take a look and see what is wrong... my start up just stays at 1s

It looks like a tall enough stack, that it won't be happy below
about 3V. The bandgap current loop also has to provide
all the gain and near saturation (as the output NPN will be until
the loop closes w/ VCC ramp) is going to be a base current
hog and gain killer. So you may have to make your startup
a little more aggressive or maybe lower the value of R4.

If you want it to work well below 2V you'd be looking
at a more folded scheme I expect.

hi... thanks for your reply... i was wondering if it has anything to do with the way i ramp my supply... i ramp it linearly from 0s to 1s to 4V. If i ramp it within 1us, then the output rises within 1us too, it follows the supply ramp. Normally, to test the start up time, how do people normally ramp the vdd and within how many seconds?

That result means that you can dynamically trigger, but
depend on a mimimum dV/dt to do it and DC is not
enough. That is bad for a general purpose application
because you don't know how slowly power might be applied -
could be sub-uS at test but tens of milliseconds in the
product application. An authoritative DC startup is very
desirable. If you can make it fail in simulation there
are armies of clueless component users who will merrily
repeat your discovery in real life, and then comes the fun.

Did you try playing with the "cutoff" resistor R4 yet?

You might try using a wilson current mirror (which has more headroom) rather than a widlar current mirror, or forgo using Q5 and Q6. If you can make Q3, Q4, Q5, Q6 and Q7 pmos, you will not have base current errors, just an idea.

I have made startups like this also. Try connecting the emitter of Qs to the base of Q1 or Q2, and use two diode connected npn in the startup

In general electronic system, 20us is used for VDD rise. It reflects the power supply is charging the input capacitor.

hi... thanks alot for all your help... i found the cause of the problem, if vdd is ramp faster lets say 1us, then 2V output will also settle in 1us. But if i ramp to 8V instead of 4V, then 2V output will settle within 500ms...

i have a new headache here. All 3 main current branches are going at 10uA. Is this practical is real circuits or do i need to burn more current... my specs is to make it work at a 1mA load. But how is Q7 going to supply a 1mA load when it is biased at 10uA? If i connect a low resistor to this output, lets say 2K, then Vout which is design to be 2V drops to 1V. How do i measure load regulation in this case and get 1mA load without letting the bandgap output to be affected?

Added after 4 hours 26 minutes:

i was thinking design a buffer but have no idea how to design a buffer for this bandgap circuit... anyone can offer some help pls...

Never put a load directly to a bandgap output node.
Usually it's weakly driven and has a high impedance
-> your voltage drops. Go with the idea of the buffer

A simple unity voltage gain buffer is sufficent. If you like
you can also do a programmable buffer for triming, without
any effect on bandgap stabilty over load. The load is driven
out of the buffer.

Best Regards

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