mvj
Advanced Member level 4
Hi All,
I am designing band gap reference block in chartered 65nm process. Across the temperature range of -40 to 85 degrees there is a total of 0.7% variation in the output voltage. I have optimised the circuit such taht the decrease in voltage to the left of the central point and the decrease in voltage to the right of the central point are almost equal i.e. is to say taht the circuit has been optimized to its best as per my knowledge. May I know if there is a way to further recude the variation of voltage (currently 0.7%) across temperature or could this be a process related thing and can not be optimized any further? I desinged a band gap reference on another process where i have achieved .04% variation in voltage across temperature, that was in another process though so I am wondering what the problem is.
Thanks a lot in advance!!
Best Regards,
M.
I am designing band gap reference block in chartered 65nm process. Across the temperature range of -40 to 85 degrees there is a total of 0.7% variation in the output voltage. I have optimised the circuit such taht the decrease in voltage to the left of the central point and the decrease in voltage to the right of the central point are almost equal i.e. is to say taht the circuit has been optimized to its best as per my knowledge. May I know if there is a way to further recude the variation of voltage (currently 0.7%) across temperature or could this be a process related thing and can not be optimized any further? I desinged a band gap reference on another process where i have achieved .04% variation in voltage across temperature, that was in another process though so I am wondering what the problem is.
Thanks a lot in advance!!
Best Regards,
M.