Dinoc
Newbie level 3
Hi all,
I have a design in which there are two sub-sections (SUB1 and SUB2) having two different clocks (CLK1 and CLK2)
SUB1 and SUB2 share a block which is clocked by CLK1 or CLK2 depending on whether SUB1 or SUB2 is using it.
I implemented a glitch free clock muxing that gives the right clock to the sub-block (SCLK) depending on who is using it.
The problem is that the clock should be balanced between the CLK1 and SCLK and between CLK2 and SCLK.
How can I say to synthesis tool that this clock has to be balanced between the two pairs of domains?
Thanks,
Dino
I have a design in which there are two sub-sections (SUB1 and SUB2) having two different clocks (CLK1 and CLK2)
SUB1 and SUB2 share a block which is clocked by CLK1 or CLK2 depending on whether SUB1 or SUB2 is using it.
I implemented a glitch free clock muxing that gives the right clock to the sub-block (SCLK) depending on who is using it.
The problem is that the clock should be balanced between the CLK1 and SCLK and between CLK2 and SCLK.
How can I say to synthesis tool that this clock has to be balanced between the two pairs of domains?
Thanks,
Dino