Neural
Newbie level 1
After elaborating my design, I execute the following:
I can't find where the erroneous reference to the fsc0g library is made. I have searched all my scripts.
I assume this is an old reference in the binary tech files, but i have nothing to support this claim however.
Therefore, my question is: what (internal) command is DC executing when I do a report_wire_load (or any other constraint related command) for the first time and cause the application of constraints and hence the information/error output?
Regards
Code:
design_vision> report_wire_load
Information: Changed wire load model for 'DFF_W_W4' from '(none)' to 'G5K'. (OPT-170)
(...)
Information: Changed wire load model for 'DFF_fall_W_W4' from '(none)' to 'G5K'. (OPT-170)
** Error: Can't find the specified library 'fsc0g_d_sc_tc.db:fsc0g_d_sc_tc' in memory. (UID-131)
** Error: Can't find the specified library 'fsc0g_d_sc_tc.db:fsc0g_d_sc_tc' in memory. (UID-131)
Information: Updating design information... (UID-85)
****************************************
Report : wire loads
(normal report follows)I can't find where the erroneous reference to the fsc0g library is made. I have searched all my scripts.
I assume this is an old reference in the binary tech files, but i have nothing to support this claim however.
Therefore, my question is: what (internal) command is DC executing when I do a report_wire_load (or any other constraint related command) for the first time and cause the application of constraints and hence the information/error output?
Regards
