Bad habit in Verilog HDL

[cafukarfoo]

Hello All,

Can you guys share some of the bad habit when we code in Verilog HDL in order to avoid bad timing during synthesis?

Thanks.

 

[gliss]

One general tip is to use a linting tool to catch bad styles, poor constructs and other mistakes.

 

[cafukarfoo]

What is linting tool mean? Any example?

 

[aji_vlsi]

What is linting tool mean? Any example?

Look at www.synopsys.com and Leda tool from them. www.atrenta.com - Spyglass

HTH
Ajeetha, CVC
www.noveldv.com

 

[vlsichipdesigner]

Dear Designer,

my 2 cents in this discussion,

Rather to discuss about the bad habits, why not discuss about what are all the good habits or good coding styles to be followed.

If we dont follow good coding styles then it becomes bad habits.

please follow the link
https://www.vlsichipdesign.com/verilog_coding_styles.html

Praise the Lord

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com

 

[barkha]

Link is good -

csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf
eesun.free.fr/DOC/VERILOG/synvlg.html

 

[sp]

this morning i face some hard-to-read verilog... i think it's bad habbits.... just MHO

doing muxing in modelling... the modelling guy do this...

assign out = sel1 ? (sel2 ? b1 : (sel3 ? (sel4 ? d1 : (sel5 ? e1 : e2)) : c2) ) : a2

arghhh... when i try to visualize and debug the design... it really make me crazy....

really....

 

[ubna]

Messing up with reg and wire in the declaration is a huge head ache...

 

[khplnarayana]

SpyGlass is one of the best tool to catch bad verilog/vhdl coding styles.

It runs pretty fast compared to traditional implementation tools.

Regards,
Narayana

 

[lubee]

the linting tools:synopsys leda and novas Nlint