I agree. If the current exceeds the rail protection clamp diodes (Vth+If*Rs) , then internal SCR latchup may damage low ESR CMOS from inductive transients or overvoltage from ESD, followed by shoothru DC thermal faults.
Normally Miller capacitance is small, and previous stage has a low enough ESR to absorb the transient. Since Cfb*ESR (or..CissRdsOn) is relative constant (for same lithography/Vds rating) this is only a real problem on unbuffered registers to inductive loads or "defective or ESD damaged" parts where ESD has closed the junction gap reducing ESR and increasing Ciss causing excessive leakage and "back-feed".
A Huntron tracker is an effective sweeping current source for isolating these faults on external pins, while ICT vector tests verify existence of any internal faults. Floating inputs can also be a cause , prey to ESD even without contact. (Technical correct term is EOS, or electrical over stress.) Even LEDs without ESD zener protection are commonly accused of being bad parts , when the user is unaware of EOS risks in their assembly and handling process. I know this from 1st hand experience.(s).
Registers and FF's are edge sensitive, so a 10ns bus glitch can toggle the state with backfeed.