Xilinx is all sv now and not providing vhdl models for anything. You're stuffed if you only have a vhdl license
That's because Xilinx expects you'll be using Vivado simulator for your simulations, which has been aggressively updating support for SV since they finally officially support it (older versions sometime around 2014-2015 had the -sv switch hidden but you could use it if you wanted to accept the chance of bugs). As Vivado's simulator is mixed mode it doesn't matter if their models are in SV and their libraries/cores have a mixture of VHDL and Verilog.
Unfortunately both Aldec and Mentor charge everyone extra for a mixed simulation license, even thought that is pretty much the standard environment now days, unless you write all your own cores or only select a core in your preferred language even if it's not the cheapest or the best option for your application. Same goes for any VIP, which can be either found as VHDL or Verilog but typically not both.
alog -sv2k12 -work <library> -na all <file>
[FONT=Courier New]config_compile_simlib -cfgopt {active_hdl.verilog.xpm:-sv2k12 -na all}[/FONT]
Thanks - I'll take a look. Being a VHDL house, though, I'm reluctant to introduce any more Verilog or SV than I need to. Our synthesizable code AND testbenches are all VHDL. We pull in verilog when forced to by Xilinx IP, we but don't need to interface to it directly.Sorry for jumping in to this discussion.
If you want to save some time and just want to verify your AXI4-Lite, I can recommend this SV IP - http://syswip.com/?p=528
since Vivado supports mixed-mode sim.
VHDL BFMs using Xilinx IPs are really less or nil. There has been endless reporting on more VHDL related support on the Xilinx forum, but it has all fallen to deaf ears.
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