I am planning to use AXI4-Stream interface as a standard interface for inter IP communication(between two IPs) with in FPGA. one IP is ADC IP which forwards samples from ADC IC to DAQ IP. second IP is DAQ IP(data acquisition IP) which gathers all samples from ADC IP. Transaction is initiated by DAQ IP.So DAQ IP must be master in my design. And it is accepting data from slave ADC IP.
But I am having a doubt that whether AXi-Stream master will capable of reading data(from slave ADC IP).
If we are considering the axi-stream master example template from xilinx,master will send(write data to slave) data not reading/receiving data.
You post makes little sense as you have not posted a real problem! Are you making assumptions, if yes, why?
Have you tried simulating your design to see if AXI-S data is being transferred or not?
The ADC IP can always wait for the tready to be HIGH from the data acquisition IP and then it can stream its accumulated data.
Axi stream is point to point, single direction. If you need response data then you'll need another connection in the other direction.
But why would you use axi streaming for this? AXI3, AXI4 or AXI4L offer bi-directional links.