AXI4 master bus functional model implementation

[tariq786]

I am looking into the following code on github. I know verilog and this code is in VHDL. So please help me make sense of it.


https://github.com/Architech-Silica.../Synthesis_Sources/AXI_master_transaction.vhd

I have a few questions from the above code

• Can you help me trace the code or what would an equivalent verilog code look like? What is connected to what?
• Can you help me make a block diagram of the code?
• what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve? What happens if it is removed?

 

[dpaul]

I didn't look into all the details, but this is what I have to say...

1> Can you help me trace the code or what would an equivalent verilog code look like? What is connected to what?
Ans: It is a fairly large amount of code and costs time. Unless you are willing to pay, I doubt anyone here will be willing to do it for free.

2> Can you help me make a block diagram of the code?
Ans: I see it is well documented - https://github.com/Architech-Silica...master/designing_a_custom_axi_master_rev1.pdf
You can easily study the VHDL entity blocks and make a connection block diagram yourself.

3> what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve? What happens if it is removed?
Ans: Generally if master and and slave are working with the same clk then the need for buffering (using FIFOs) does not arise. But there might be other reasons (as I didn't look deeply into the code).

Note that they are using a BFM to which the AXI Master is connected. This is different from a 'real' slave connected to the AXI Master.

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If you are just learning how AXI master and slaves work, then I would recommend this:
https://github.com/ShepardSiegel/hotline/tree/master/doc/axi_examples