prashanthaditya
Junior Member level 3
I am designing a SDRAM controller with AXI interface. Right now am using only one bank for read and write upto a burst length of 4.
1. How I should modify my code such that I can have the control on all the four banks.
i.e: when one bank is writing or reading the data, I want to activate other bank or precharge other bank.
2. Can any body tell me whether the address generation block and bank management logic will be combi or sequential?
Thanking you all in advance.
1. How I should modify my code such that I can have the control on all the four banks.
i.e: when one bank is writing or reading the data, I want to activate other bank or precharge other bank.
2. Can any body tell me whether the address generation block and bank management logic will be combi or sequential?
Thanking you all in advance.