looking at the diagram again, it looks like there is a few cycles of latency between when something happens and when something changes in that status. it looks like the value changes a total of three times. I can't see the first value, but it is probably all 0's. the next value looks like bit 80 is set. the final value has both set.
I notice that awready is asserted while awvalid is 'X'. Perhaps this error condition results in an issue with the simulation aspects of this checker.