heartfree
Advanced Member level 4
site:www.edaboard.com formality set svf
I have some questions about formality(rtl vs. gate(DC netlist) need your help. The Design is around 2M gate count. Thanks.
1. How to use arithmetic generator?
I have some multipler in my RTL, like:
assign c = a * b;
2. I used ”set_svf default.svf" in script, but when doing "match", formality give me a warning --"Warning: Could not process object(s) referenced in SVF (FM-340)", actually after match finished, all compare points are match except some clock gating cell (I have set "verification_clock_gate_hold_mode" to any).
When I report unmatched points with “-datapath", there are some unmatched datapath blocks( all these blocks have multipler in their RTL, like A * B);
I am confused with these warning. can you give me a help?
thanks
I have some questions about formality(rtl vs. gate(DC netlist) need your help. The Design is around 2M gate count. Thanks.
1. How to use arithmetic generator?
I have some multipler in my RTL, like:
assign c = a * b;
2. I used ”set_svf default.svf" in script, but when doing "match", formality give me a warning --"Warning: Could not process object(s) referenced in SVF (FM-340)", actually after match finished, all compare points are match except some clock gating cell (I have set "verification_clock_gate_hold_mode" to any).
When I report unmatched points with “-datapath", there are some unmatched datapath blocks( all these blocks have multipler in their RTL, like A * B);
I am confused with these warning. can you give me a help?
thanks