gkreehal
Newbie level 2
Hi,
I need to write an interface(bridge) between the Avalon MM and APB bus. I have the follwoing signals
Avalon MM (Master) APB (Slave)
------------------- ---------------
Clk ---->
Reset ---->
(32) Address ---> PADDR -----> (16)
Write ---> PWRITE
Read --->
(32) WData ----> PWDATA ---> (32)
(32) RData <---- PRDATA <---- (32)
Wait <---- PRREADY <-----
Valid <---- PSLVERR <-----
Could someone please help me on what will go into the architecture (VHDL ) code here ?
Any examples would help me........
Thanks
- Sharon
I need to write an interface(bridge) between the Avalon MM and APB bus. I have the follwoing signals
Avalon MM (Master) APB (Slave)
------------------- ---------------
Clk ---->
Reset ---->
(32) Address ---> PADDR -----> (16)
Write ---> PWRITE
Read --->
(32) WData ----> PWDATA ---> (32)
(32) RData <---- PRDATA <---- (32)
Wait <---- PRREADY <-----
Valid <---- PSLVERR <-----
Could someone please help me on what will go into the architecture (VHDL ) code here ?
Any examples would help me........
Thanks
- Sharon