autorefresh in sdram interface?

[ahgu]

since sdram access is synchronous, and you know how many clk cycles you need for the data to come out. What if at the instant when you do a read, the controller is doing a refresh, would that delay the data available couple cycles? how would you compensate that?

I understand autorefresh is something you have to do certain times per ms.

thanks
ahgu

 

[wfond]

There are some allowable cycles for that (safety range). The case you raised, is O.K. if it's the typical factor you design with. not m@x. nor min.

 

[ahgu]

could you please give me more detail?
How to avoid the autorefresh timing difference without resort to asynchronous method?

Also, in DDR, when the host is running at 1/2 of the clk speed, it cannot access data at the full Bandwidth anyway, how would ddr help?

thanks
ahgu

 

[maskrom]

Auto-Refresh is command. In the datasheet, you will see the m@x refresh cycle time is around 16ms to 64ms. And you will see in refresh cycle time, you must preform how many time autorefresh. Like 16ms will be 1k refresh ( k=1024 ),32ms is 2k refresh and 64ms is 4k refresh. You must execute precharge all first and then do auto-refresh. Precharge must spend 1~3 cycles.each time, you do auto-refresh, 1~3 cycles is panic. But you can use burst refresh,then you can save nk X prechage time. The penality is system must wait for burst refresh cycle end. I think you will choose distribute refresh, 15.6us = 64ms/4096 will have one refresh. I hope this will answer your first question.

 

[maziar]

have any one src work mcu and sdram ?