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Automatic Layout Generation tool

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virtuoso xl layout generation

Dear All,
I'm designing an asynchronous circuit based on Martin methode (, the problem is the method's output is a CMOS circuit, I mean a switch-level description of my design. So, the problem is how can I automatically generate a layout from my switch-level description and how the sizing, routing and etc. will be solved.

Any Idea

I'm not familiar with asynchronous design but I assume you're still using standard logic gates such as AND, OR, etc... If so, your best bet might be to map your netlist into the cells of some standard cell library such as AMI or ATMEL. Once you do that, the process would be the same as for a synchronous design. You need to find a place and route tool and do the place and route.

If you don't go the standard cell route you'd have to generate custom cells with all of the associated views that are required for the place and route tools.


Hi radix,
the problem is some of my switch-level description could not be mapped to gates!! So, I need to generate layout and views as you said. My question is if there is any tools to automate or assist this process?


The last time I had to do this was about 4-5 years and I did the cell layouts manually. This approach isn't to bad as long as you don't have to do a whole lot of cells. The toughest thing is probably finding the layout design rules for the process that you're going to.

Once you have a layout that passes DRC, the place and route tool should have the tools to allow you to generate the cell views that you need in order to do the place and route of the chip.


Look the Neocell.
But If you are good in scripting,have some time, the good idea might be to write the layout generator based on the usage of basic leaf elements. The result may be compacted using some "commercial" compactor.
If you keep it simple and generate the blocks of a constrained height,
you may get a good results

you can try the tools in ic4.46 from c@dence.

in this package,a tools named virtuoso-xl can generate the layout from the circults's schematic and your own leaf componets's layouts,then you can P&R by yourself or use the other tools like icc. those is suit for both digital and analog circuits.
the only thing you have to do is writing some TF line by yourself and writing some leaf componets's layout,and introduce the tools how to generae the layout, For your swicth circuits,i think it is not a problem.
good luck.

Try Mentor Graphics' IC design Flow or Novas Laker or CADexterity's UFO. all of their's have cell generator. UFO is the best but not available.

For Mentor you can use this one :
**broken link removed**


Who used neocell? Any comments on it?

Does Neocell is a schematic to layout translation tools?? :)

By the way, do we still need virtuso XL or virtusio to edit the layout after using neocell ?? Sorry that I am not familiar with the difference between Virtuso and VirtusoXL...:)

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