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[SOLVED] automatic functions with static storage

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hulk789

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What are automatic functions with static storage in system verilog
with example
 

ads-ee

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That isn't the LRM that was ratified. The actual System Verilog LRM: IEEE 1800-2012 can be downloaded for free thru the Get program from the .
 

dpaul

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Thanks for pointing it out ads-ee, my mistake. The actual LRM is the IEEE doc.
What I posted is Accellera’s SV guide.
 

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Technically it isn't an SV guide, Acellera was the group responsible for drafting the SV extensions to Verilog. It was supposed to be incorporated into Verilog, but somewhere along the line everyone thought that SV was the new language instead of Verilog with new stuff.

So basically the Accellera SV 3.1a extensions may be different than what is in IEEE SV 1800-2012, but exactly what might be different I don't know, as I haven't gone through both side by side.
 

dave_59

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So basically the Accellera SV 3.1a extensions may be different than what is in IEEE SV 1800-2012, but exactly what might be different I don't know, as I haven't gone through both side by side.
All Accellera or IEEE SystemVerilog LRMs prior to the 1800-2009 LRM were just a set of extensions to the existing Verilog IEEE 1364 LRM. A lot of interactions between SystemVerilog and Verilog were left unspecified. The 1800-2009 merged the two documents into one, and the latest 1800-2012 LRM is corrections and a few more additions.

To answer the OP's question, any function declared inside a class as a method is an automatic function, and can have a static variable.

Code:
class A;
  local int m_i;
  static int count; // static class member
  function new;
     count++; // counts the numbers of time this class is constructed
  function void set_i(int i);
    static int count; // static variable inside an automatic function
     m_i = i;
     count++; // counts the number of times this method gets called
  endfunction
endclass
A static variable inside a method is no different than a static class member - it just has more localized scope

Because of legacy with the Verilog 1364-1995 LRM, all functions declared outside of a class default to a static lifetime. In the original Verilog LRM, all variables were static; there were no automatic variables or functions. In most modern programming languages, all functions have automatic lifetimes. The reason for wanting to have a static variable inside a automatic function is no different than wanting a static variable anywhere else. Declaring it inside the function just gives you a name that is local to the function scope.
 
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