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All Accellera or IEEE SystemVerilog LRMs prior to the 1800-2009 LRM were just a set of extensions to the existing Verilog IEEE 1364 LRM. A lot of interactions between SystemVerilog and Verilog were left unspecified. The 1800-2009 merged the two documents into one, and the latest 1800-2012 LRM is corrections and a few more additions.So basically the Accellera SV 3.1a extensions may be different than what is in IEEE SV 1800-2012, but exactly what might be different I don't know, as I haven't gone through both side by side.
class A;
local int m_i;
static int count; // static class member
function new;
count++; // counts the numbers of time this class is constructed
function void set_i(int i);
static int count; // static variable inside an automatic function
m_i = i;
count++; // counts the number of times this method gets called
endfunction
endclass