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automatic cache netlist generation??

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zorjak

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Hello guys,

I am new in field of processor design.

currently I am researching memory design part so I was wondering this. Is there some tool that on the market that is used for automatic HSPICE netlist generation. for example automatic hspice netlist generation of L1 cache. for example GUI that demands definition of sram cell type, sense amplifier, decoder type, cache associativity... and it generates HSPICE netlist of it?

I am totally new in this field so I was just wondering is there any tool like this.

If someone knows anything like this I would be very grateful if he (she) tells me.

Thanks
Zorjak
 

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