I don't have time to look up the part support for Vivado right now, but the information is available on Xilinx's website, but I don't believe that 6Q is supported in Vivado. Vivado was designed for 7 series and beyond. Everything prior to 7 series is only supported on ISE.
The synthesis failed message may be due to cores being generated in a different family on a different tool platform. You may have to generate new IP cores in Vivado for V7Q for it to work properly. I vaguely recall being told by the FAE to generate new IP cores when I migrated a design from K6 to K7 years ago