[SOLVED] Attatching SDR SDRAM chip to Cyclone IV Processor

[nkinar]

For an application that requires the storage of data from an array of microphones, I need to interface an SDR SDRAM to a Cyclone IV FPGA.

The FPGA is an Altera Cyclone IV (EP4CE15F17I8LN), and the SDR SDRAM is the Micron MT48LC16M16A2BG-75 IT TR.

A datasheet for the Micron part is available (https://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf).

While researching a solution, I've stumbled across the following application note from Altera detailing an example SDR SDRAM controller (Download SDR SDRAM Controller).

I am wondering if someone could comment with regard to these four questions:

(1) Should I use the SDRAM controller in the Altera application note, or can I use the ALTMEMPHY controller? Is the ALTMEMPHY controller available for "free" for a user of the Web Edition Quartus II toolset, or must a licensing fee be paid before a configuration device can be programmed?

(2) If I use the SDR SDRAM controller detailed in the application note, how do I set up the pin assignments for linking the FPGA to the SDRAM? Can I use any pins on the FPGA, or are there specific pins to be used?

(3) Is there another (perhaps better) way to interface the SDRAM to the FPGA?

(4) Does the Altera application note SDRAM controller work well? I am using the FPGA for a research application, and I would like to avoid using paid IP ;-)

 

[shreyas_patel21]

which board you are using for cyclone 4
use pin assignments as per that board.

you should use sdram controller

Altera application note SDRAM controller works well

 

[nkinar]

Thanks, shreyas_patel21; it is good to know that the Altera application note Verilog code works well!

I am not using a development board for Cyclone 4, since I've had to design my own hardware for this research system. The Cyclone 4 handbook contains information about using specific pins for SDRAM interfacing, but I am wondering if this is also the case for SDR SDRAM.

Do I need to assign the SDR SDRAM to specific pins on the FPGA, and if so, where can I find information on this pin mapping? Is a particular section of the Cyclone 4 handbook relevant in this situation, or is there another example somewhere that I can look at?

 

[elec4fun]

Hello,

You don't have to use specific pins for SDR SDRAM (except for the memory clock where you'll use a pll output pin).

 

[nkinar]

Thanks, crevars; that makes it more simple for me. I will use the SDR SDRAM implementation given in the Altera application note, and I will only use a PLL output pin for the SDRAM clock. Many thanks!