ATPG Pattern Simulation

[dft123]

Hi
I am new to the field of Scan/ATPG and I have just taken a tutorial to scan insert + atpg + pattern simulation for a simple 8 bit RISC processor. I am done with the first 2 steps. I have used Mentor DFTA (insertion) and FS(atpg). Now I want to validate the patterns through simulation.

Is it possible to simulate the atpg patterns generated by Fastscan by using VCS?
What are the steps involved in doing this VCS simulation?

Regards

 

[rca]

yes you could simulate.
normaly the atpg tool could generate a verilog test bench that read an input file that contains the scan vector and compare with an other file which contains the output scan vector. So you have the test bench from the ATPG tool, the netlist used by this atpg for the DUT and a sdf file for timing annotations.