[SOLVED] ATPG Help required for post silicon debug

[ananthashayanams]

Hi

I am involved in generating ATPG patterns for a relatively big chip making these patterns work on real Silicon. The problem is, the chain test is failing as well as scan test in the ATE. If the results are looked then it's coming from 8 chains and these are causing the failures in both Shift & Capture.

I want to make sure my Shift passes. I tried adjusting the clock which goes into the error block, strobing it +/- 4 cycles but nothing changed , Tried from 1MHz - 40 MHz and the failures are the same. Looks like some real failures.

Could anybody suggest me anything at this juncture to move ahead and try making these shift patterns pass. Anything to take care during pattern generation.

btw the tool used is Mentor TestKompress with EDT on

 

[rca]

Did you simulate the serial patterns with the final netlist and with timing to check?
I believe all your timing setup & hold are met, as well the logic equivalent checks.
I believe you have regenerate the patterns with the latest netlist, some PR tools could move the scan element along the scan chain or between scan chains?

 

[ananthashayanams]

Well the chip is very big and it's difficult to do a full chip simulation of the serial patterns with the hardware infrastructure we have.

However the patterns have been generated using the latest netlists. What do you mean when you say some PR tools could move the scan element along the chain or between the chain.

 

[rca]

For example EDI tool changed the scan element order in the scan chain to reduce the routing length. It could also swap scan element from one scan chain to another one to alone reduce the routing length due to the scan chain connection.

Just to confirm the timing is clean as well?

---------- Post added at 10:40 ---------- Previous post was at 10:37 ----------

Did you check the timing is clean for the test kompress module?

 

[haykp]

May it be that reset signal is being keep on active value during ATPG pattern, think if you ( or tool not sure) have chosen the reset active value not right, then this will bring to failure.

 

[ananthashayanams]

Hi Haykp

The rest signal is fine & in line with other passing blocks as seen from the testproc file, This issue is seen only with a particular block and the similar blocks of this type are all passing. I tried to isolate if this could be an hardware issue but both sorted and packaged parts numbering around 40 have the same identical results.

@rca : the flop count is > 5 million
The timing is clean for that particular block stand alone.

 

[haykp]

Frankly I dont think that this is a hardware issue because the error is seen in Shift & Capture phase, otherwise if it was a hardware issue then the issue would be seen in capture phase. Or may be not...
Are you running parallel or serial test?

 

[ananthashayanams]

Hi

The real issue was with a wrong netlist provided from the PD team. By mistake the wrong file for that particular block had been checked in which had a missing flop as against the latest. This was causing the issue. I boiled down to the flop which was missing and when the newer netlist was used to generate patterns, chain test passed comfortably.

Thanks all for the support