Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
i cant understand the working of the following circuit..
it is said that "The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects."..
please say me how it works... thanks in advance..
thank you skogsjanne ... i really need to understand it... i tried to draw the timing diagram but i am not getting it properly since a level and edge triggered latch are connected together... can u please show me the timing diagram ?
In the synchronizer the edge triggered flipflopp probably has a very short (or negative) setup time but a longer hold time. The level triggered latch is used to satisfy those requirements.
Since we don't have the setup and hold times we only know that Tn will be available to the edge detector after between approximately one half and one clkIO cycle time.
This is slightly smarter than having two edge triggered flippflopps in the synchronizer.
The latch is transparent when clkIO is high and will latch the level when clkIO is low.
The edge triggered flippflopp will transfer the input to the output on the rising edge of clkIO.
If Tn change state when clkIO rise it will take one clkIO cycle until it reach the output.
If Tn change state just before the falling edge of clkIO it will take one half clkIO cycle until it reach the output.