ATLYS FPGA kit, how to light a LED ?

[ali8]

Hello,

I have an ATLYS FPGA kit, and use ISE 13.1, and I have this code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simple is
    Port ( A : in  STD_LOGIC; Z : out  STD_LOGIC);
end Simple;

architecture arch_simple of Simple is
begin
    process(A)
    begin
        if (A=1) then
			Z <= '1'; 
	else
			Z <= '0';
	end if;
    end process;
end arch_simple;

I want "A" to be SW0 ( A10 ), and "Z" to be LED0 ( U18 ), so
when the switch is on, the LED is on, and vice versa.

I cannot figure out how to do it, any help is appreciated.

-Ali

 

[mrflibble]

You need a .ucf file to specify the pins for the inputs and outputs. You can download the .ucf from digilent.

Also, you may want to pick more meaningful names than A and Z... If it's a switch, call it that. If it's a led, call it that.

 

[ali8]

Thanks for the quick response : )

In the .ucr I can see:

NET "sw<0>" LOC = "A10";

So suppose my input switch is named S, what should I do?

Should I modify this code so that it's:

NET "sw<0>" LOC = "S";

?

 

[mrflibble]

If you want to name your switch "S", then the .ucf entry for that would be:

NET "S" LOC = "A10";

The "S" in this case being the net name, and the A10 being the pin number on the fpga.

Similarly you can do this:

NET "LED" LOC="U18";

 

[ali8]

Thanks, that's what I wanted :smile: I will get back here if I needed any further help.. :wink:

 

[ali8]

Hi,

In the ref. manual they mentioned the following:

"If programming with a .bit file, the startup clock must be set to CCLK."

Well, clearly ISE 13 will generate a .bit file...So, any idea how can I do this?

 

[mrflibble]

Hi,

In the ref. manual they mentioned the following:

"If programming with a .bit file, the startup clock must be set to CCLK."

Well, clearly ISE 13 will generate a .bit file...So, any idea how can I do this?

By reading the FAQ?

Digilent Inc. - Digital Design Engineer's Source

When I am using Export to program an FPGA I receive the error "startup clock for this file is CCLK instead of JTAG-CLK, problems will likely occur." What do I do?

The configuration state machine inside the FPGA needs a "startup clock" to clock the final startup sequence after configuration. The startup clock source is controlled by an option setting in the "Generate Program File" process in the Xilinx ISE Project Navigator tool. The clock source should be set to JTAG-CLK to create a .bit file to be used for configuring the FPGA using a JTAG interface. The clock source should be set to CCLK for .bit files that are intended to be programmed into a Platform Flash.

When building the project make sure that the startup clock is set appropriately. You can do this in Project Navigator by right clicking on the "Generate Program File" process. Select Properties and then click Startup Options. Set the startup clock to JTAG-CLK or CCLK as appropriate.

The Xilinx iMPACT tool is capable of automatically setting the statup clock bit to JTAG-CLK if necessary during the programming process. Adept isn't capable of changing the clock source "on the fly" and the programming file must be built with the correct setting.

Personally I have never had to bother setting this option to get it working on my atlys board. Everything worked just fine with the default ISE settings for generating the .bit file.

 

[ali8]

After reading "Xillinx® ISE WebPACK VHDL Tutorial", I changed the setting
of the "FPGA Start-Up Clock" from CCLK to JTAG-Clock, because I am using
the PC to program the FPGA...

Well, finally, It worked ! :grin::grin:

Thanks mrflibble, I appreciate your help.