ATCA and Advacned Switch based on PCI-express

[alex_fn]

hello ,are there some guys intrested in AS -advanced switching ,ASI is the next step in IO technology
Advanced routing, scalability, distributed computing, high-availability (HA), protocol agnostic switching
ASI and PCI Express are complimentary
ASI extends the application space for PCI Express
ASI as the backplane interconnect, PCI Express on the planar
ASI is software compatible
Legacy PCI compatibility via PI8
Generic legacy load/store compatibility via SLS
Socket communication compatibility via SQ and SDT
ASI is key to platform evolution
Satisfy the next generation interconnect requirements for next communications, compute, storage and embedded platforms
Load/store and socket communication models via a single switched fabric interconnect.
[/img]

 

[alex_fn]

The Merchant “Standard” Interconnect:

ASIC “In-House”
Originally the only option for OEMs
Still used for highly custom applications
--------------------------------------
Merchant Proprietary
Started the process of interconnect outsourcing
No ecosystem stunted market

-----------------------------------------------------
Merchant Standard
Enables OEM independence
Example Standards – ASI, PCIe, I/B & Ethernet

Added after 2 minutes:

PCIe Limitations:


No “multi-protocol” support
No peer-to-peer communication
Peer-to-peer definition
Cooperating distributed processing units
No centralized control
No hierarchical organization
Requires hierarchical structure for configuration (Upstream/Downstream)
Reset distribution from Root Complex
Interrupts only routed to the Root Complex
No support for redundant routing
No protection
No multicast
No support for hot join

Added after 1 minutes:

Ethernet
(as an interconnect)

------------------------------------------------------------
Legacy SW compatibility for Peer-to-Peer
Large ecosystem
Low Cost Processor inefficient at Multi-gigabit
Latency and Quality of Service limitations

 

[alex_fn]

AS introductions

 

[alex_fn]

The Advanced Switching Advantage
The candidates for high-speed interconnect include several different technologies, such as Advanced Switching Interconnect (ASI), Ethernet, InfiniBand, Serial Rapid I/O (sRIO) and PCI Express (PCIe). During the development of PCI Express, the technical contributors to this specification ensured its extensibility by layering the protocol for future advancements. Advanced Switching is the first such extension. It shares the same physical and data link layers as PCI Express, which allows it to leverage the readily available and well understood IP that has been extensively verified and tested for interoperability.
In addition, ASI maps seamlessly to any industry-defined PCI Express form-factor, such as Advanced TCA, AMC and ExpressModule. The additional capabilities of ASI are realized by enhancements to the transaction layer. These features include support for multiple hosts, true peer-to-peer communications, legacy compatibility, I/O virtualization, topology agnosticism, flexible protocol encapsulation, multicast transport, redundant connections and additional quality of service (QoS) and flow control mechanisms. By adding these capabilities, ASI expands the application space for PCI Express in compute, storage and communication systems.

Legacy Compatibility

Advanced Switching utilizes a concept known as protocol interface (PI) for supporting different types of data movement within the interconnect. There are three types of PIs: services, native and tunneling, also known as encapsulation. The first encapsulation PI is PI-8, which facilitates tunneling of PCI Express traffic through an ASI fabric. Under this model, multiple virtual PCI Express hierarchies are formed within a common ASI fabric, each with a host CPU controlling one or more I/O devices and running legacy software.

The PI-8 architecture allows balancing of computational and I/O requirements and increases platform availability and serviceability. In addition, it allows the expansion of PCI Express over extended distances, typically up to 10 meters over copper, through ASI. Optical implementations have been shown to operate ASI x4 links over a distance of 100 meters. Another important advantage is that the use of PI-8 does not preclude the co-existence of ASI traffic over the same fabric.

Added after 5 minutes:

Flexible Data Movement

Through the PI mechanism, ASI provides orthogonal data movement models that are tailored for specific communication policies. Advanced Switching Interconnect is the only fabric that provides a simple load/store (SLS) model for data movement, i.e., PI-10. The SLS model is an adaptation of protocols that use a read/write mechanism for data transfers, which does not require a copy of original data sent to an intermediate buffer previous to a transfer.

In addition, PI-11 specifies the data movement PI for simple queuing (SQ), which provides a simple messaging model for packet-based communication using familiar push/pull queue modeling. Socket data transfer, designated by P-9, is a mechanism that provides data synchronization and movement models for TCP socket-based connections. PI-2 represents the ASI model for generic data movement and includes segmentation-and reassembly (SAR) capabilities for packets larger than a specified ASI maximum packet size. Advanced Switching also supports the concept of software-based PIs. This allows software to construct packets that support other ASI protocol interfaces or a proprietary protocol interface.

Trusted Peer-to-Peer Communications

Advanced Switching allows several methods of peer-to-peer communication. One of these is through the mapping of local memory space in multiple computing domains using apertures, a component of the SLS model. Apertures are “windows” into memory from one peer entity to another, which are protected by various security mechanisms. These mechanisms include path protection, access keys and sequence numbering to ensure a trusted path between totally monolithic or peered ASI endpoints.

In the unlikely event of an error, ASI utilizes error detection and reporting far in advance of most fabrics available today. Event reporting is targeted for link cyclic redundancy check (CRC), packet CRC and invalid sequencing, among others. A true peer-to-peer relationship is facilitated in that there is no concept of an upstream or downstream bridge in the routing of ASI packets. There is only a notion of source and terminus. Peer-to-peer communication can also be achieved using the SQ model. This is useful for short messages notifying CPUs of pending DMA transfers or other operations

Added after 1 minutes:

Using data movement protocols like SQ and SLS, it is possible to open up an aperture into any other CPU’s local memory and perform operations such as, but not limited to, placing a message in that CPU’s local queue indicating that data is ready to be transferred, then offloading that data transfer to a trusted path element in the fabric. This completely removes the target CPU’s interaction until the transfer is complete. In fact, the aperture mapping mechanism included in native SLS allows any intelligent ASI endpoint to access any other ASI endpoint in a given fabric. This can be leveraged by utilizing ASI bridging on existing PCI Express-enabled devices, giving those devices the same ability as a native ASI endpoint.

Protocol Agnosticism

Advanced Switching’s protocol encapsulation is not limited to PCI Express. A mixture of protocols can be simultaneously tunneled through a single ASI fabric, making it a powerful and desirable feature for next-generation modular applications such as multi-service routers and embedded compute platforms. Advanced Switching’s path-based routing architecture allows it to be protocol-agnostic, since switches only require an 8-byte header to route packets. With this feature, applications currently using low performance proprietary protocols can be upgraded to ASI switching, and backward software compatibility can be maintained by tunneling of the existing protocols.

Multicast Communication

Not to be confused with the Ethernet broadcasting model, ASI supports true multicasting via multicast group IDs. This allows the combination of multiple endpoints that are targeted to receive the same traffic into a single packet delivery at the source, rather than sequentially sending redundant packets to individual endpoints. Endpoints not considered members of a group can be excluded from receiving unsubscribed multicast group traffic, while unicast packets can still be sent to non-targeted endpoints concurrently with the multicast traffic. Any member of a given multicast group can be made a source or destination of the group. This feature becomes interesting in applications such as video and audio teleconferencing, or other applications where multiple endpoints need to receive duplicate data from a common source.

I/O Virtualization

The concept of disaggregated I/O contrasts with the concept of I/O virtualization. Disaggregated I/O is accomplished with the tunneling of PCI Express through a single ASI fabric. In this model, multiple PCI Express hierarchies share a common ASI interconnect, but within each hierarchy a single host-to-I/O relationship remains.

In I/O virtualization, a single I/O endpoint has the intelligence necessary to service several CPUs by monitoring handles assigned to its usage from the different compute elements. A single I/O device is given tasks by multiple CPUs and can operate on those tasks in the most efficient manner, as programmed. These individual tasks can be subsets of a larger operation, thereby allowing asynchronous parallel multitasking. Each task or subtask is given a handle associated with a target CPU, and the I/O device returns the results of a given task to the assigned target. In this way, data flows can be maintained at an optimum level since tasks can be performed asynchronously, resulting in a more efficient use of both the I/O device and the fabric.

Advanced Switching provides for disaggregated I/O and virtualized I/O by allowing low latency, path-based routing from source to terminus. Additionally, the data movement models already discussed allow highly efficient CPU-to-CPU and CPU-to-I/O communication. The protocol agnosticism of ASI allows the simultaneous transportation of differing I/O protocols through the fabric. Protection mechanisms of ASI allow data to flow from endpoint to endpoint, and ensure that it is only delivered to the correct terminus point in the fabric. These factors lead to a design where I/O can be completely disaggregated from the compute elements of a given system .

Robust QoS

Advanced Switching offers extensive QoS through various components, including different service levels for traffic flows and congestion management. Traffic classes are logical entities that are mapped to physical virtual channels (VCs). Up to 16 unicast and 4 multicast VCs are specified in ASI. Credit-based flow control delivers a link-level-like flow control mechanism between two interconnected ASI devices. This flow control is available for each individual VC of a port, resulting in effective QoS between traffic types.

Added after 1 minutes:

Status-based flow control, unique to ASI, is a more granular flow control mechanism that is relative to the VC of the particular segment and also to the VC of the next destination segment. It is initiated at the egress or output of the interface back toward the previous segment. This allows a more sophisticated mechanism for minimizing head-of-line blocking for one-, two- or three-stage fabric topologies. Injection rate limiting provides connection queues for flow isolation at a packet source enabling fine-grained rate adaptation.

Scalability

Advanced Switching fabrics allow hot-swapping and “hot-joining” endpoints. The endpoint can be a single I/O or compute device, or a completely monolithic system consisting of a root complex, memory and I/O, running under an entirely different operating system than the system to which it is being connected. This is achieved by adding a “DL_PROTECTED” state to the data link (DL) engine just above the physical layer. If an endpoint is hot-swapped or hot-joined, the DL layer detects this as a fabric event, and places the link in a protected state. In this state the physical layers connect and exchange link information. Once the link is up and verified, ASI message events, designated by PI-5, are allowed through the link in order to let a fabric manager verify the new endpoint and resources. Once the new endpoint is verified, the DL returns from a protected state to an active state.

If the new endpoint is a complete system also running a fabric manager, the implementer has multiple options for how to proceed. One possibility is that the two systems can act as independent, monolithic entities that share the same fabric. In this case, they merely share resources based on the data movement apertures outlined in the SLS protocol by their respective fabric managers. Another possibility is that one system can take “ownership” of another. This is accomplished by initiating a spanning tree election in order to determine the primary fabric manager. Once this is determined, data is exchanged to allow proper data movement through the fabric to its new set of endpoints.

Thus, using the hot-swap and hot-join features of ASI allows a scalable fabric that can be designed to facilitate the system expansion, monitoring and flexibility needed in complex compute environments.

Redundancy

Redundancy in a fabric interconnect is envisioned using duplicated topologies. Advanced Switching allows active-passive and active-active designs using star, dual-star, meshes and completely unique implementations of fabric topologies. The use of primary and secondary fabric managers, as well as ASI event messaging, allow failover mechanisms to be implemented covering minor to catastrophic fabric events. Data movement models for performing dual casting of packets through separate fabrics to the same terminus are available. Additionally, SLS apertures can be configured to allow primary and secondary paths through a given fabric, or its redundant partner for packets to route to their target endpoints. This makes ASI an excellent candidate where redundancy in a system is required.
Advanced Switching Interconnect technology can be implemented at the blade or backplane level in compute, storage or communications systems (Figure 4). The benefits of ASI are many for applications ranging from small embedded systems to large compute platforms.

Added after 59 minutes:

Peer To Peer Communication

 

[alex_fn]

A comparsion of Advacned Switch & Pci-e from PLX,

 

[openwindows]

yes,i am interested in ASI.

you are researching it?

Added after 1 minutes:

https://developer.intel.com/netcomms/as/collateral.htm

 

[alex_fn]

thanks your good link,
and yes ,i am studying that recently,

i have found a book <PeerToPeer Computing >..

 

[amon]

Any clue on how to get the full AS specification?. Thx

Amon

 

[skaw2000]

it is here.

www.buswares.com

download it after register

 

[wilbert_hj]

is there anyone who implement ASI using Xilinx FPGA?