I used an asynchronous ROM in one of my FPGA design a few monthes ago.But i found that in most occasions synchronous ROM is used,and i am trying to transform my desgin to ASIC.
If i change it to synchronous ROM,a lot of timming schedules will be changed and this will cost much time.
Do i need to change it to synchronous ROM??
The fact is
that in modern FPGAs the medium volume ROMs are usually synchronous ones
because they are built in synchronous RAMs.
If you do not use such ROMs and FPGAs
then it does not matter.
But in FPGA synchronous ROM is preferable
because of pipelining,
false path removing,
etc.