asynchronous FIFO with different resets for write & read

[sun_ray]

In this attached paper the asynchronous FIFO shows two resets, one for write and another for read. How to take care of two different independent resets as shown in this paper?

Suppose this asynchronous FIFO is being used inside another top level design where the top level design has only one reset. How to take care of these two independent reset of this asynchronous FIFO then?

Regards

 

[FvM]

As discussed under 5.5 Multi-bit asynchronous reset, synchronous removal related to the respective clock is required for each reset signal.

 

[sun_ray]

As discussed under 5.5 Multi-bit asynchronous reset, synchronous removal related to the respective clock is required for each reset signal.

But our problem is our top level design where this asynchronous FIFO is instantiated has only one reset. Should then both the write and read resets be connected with each other and then the connected wire connecting both the write and read resets be connected with the top level module single reset?

The problem here is that the top level has only one input for reset and the FIFO has two independent resets. How to take care now?

Regards

 

[FvM]

You'll add state-of-the-art reset synchronizers for both clock domains.

 

[sun_ray]

This paper shows the grey coded output from the write pointer is being directly compared with the grey coded output from the read counter. It does not show that grey coded output passing from one domain to another domain with double stage synchronizer. An asynchronous FIFO should have the synchronizers to pass the write pointer to read domain for comparison. But this paper does not do that.

 

[FvM]

The paper does, see 6.3 and 6.4.