Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Asynchronous fifo solve the error

Status
Not open for further replies.

sai685

Junior Member level 2
Joined
Sep 4, 2015
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
292

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
module fifo_top
    #(
    parameter DEPTH = 32,
    WIDTH = 32,
    ADDR = 5
    )
    (
    input wire write, wreset_b, wclk, read, rreset_b, rclk,
    input wire [WIDTH-1:0] wdata,
    output wire [WIDTH-1:0] rdata,
    output wire rempty, wfull
    );
    
    // function to convert from gray to binary
    function [ADDR:0] G2B_Fn;
    input [ADDR:0] gray;
 reg [ADDR:0] binary;
    integer i;
    begin
    binary[ADDR] = gray [ADDR]; 
    for (i=ADDR-1;i >= 0;i=i-1)
   binary[i+1] = (binary[i] ^ gray[i+1]);
    
    G2B_Fn = binary;
    end 
    endfunction
    
    // declare connecting wires
    wire [ADDR:0]   wptr_b,wptr_g,  // binary and gray signals from write pointer
                    rptr_b,rptr_g;  // binary and gray signals from read pointer
    
    reg [ADDR:0]   g2b_wd_op,           // function G2B_Fn output in the write domain
                    g2b_rd_op;          // function G2B_Fn output in the read domain
    wire [ADDR:0]   g2b_wd_ip,          // function G2B_Fn input in the write domain
                    g2b_rd_ip;          // function G2B_Fn input in the read domain
    
    //assign intermediate wires
    always @(g2b_wd_ip or g2b_rd_ip)
        begin
            g2b_wd_op = G2B_Fn(g2b_wd_ip);  
        g2b_rd_op = G2B_Fn(g2b_rd_ip);
        end
    // instantiate write pointer
    pointer wptr(
    .clk(wclk),
    .reset_b(wreset_b),
    .op(write),
    .fifo_status(wfull),
    .gray(wptr_g),
    .binary(wptr_b)
    );
    
    //instantiate read pointer
    pointer rptr(
    .clk(rclk),
    .reset_b(rreset_b),
    .op(read),
    .fifo_status(rempty),
    .gray(rptr_g),
    .binary(rptr_b)
    );
                    
    //instantiate memory module
        memory m1(
        .clk(wclk),
        .reset_b(wreset_b),
        .write(write),
        .wfull(wfull),
        .waddr(wptr_b[ADDR-1:0]),
        .raddr(rptr_b[ADDR-1:0]),
        .wdata(wdata),
        .rdata(rdata)
        ); 
    
    
    //instantiate read->write synchronizer
    sync_r2w syncr2w(
    .clk(wclk),
    .reset_b(wreset_b),
    .rptr(rptr_g),
    .rptr_wr(g2b_wd_ip)
    );
    
    //instantiate write->read synchronizer
    sync_w2r syncw2r(
    .clk(rclk),
    .reset_b(rreset_b),
    .wptr(wptr_g),
    .wptr_rd(g2b_rd_ip)
    );
    
        
    //instantiate write domain comparator
    compare_wr cmp_wr(
    .rptr(g2b_wd_op),
    .wptr(wptr_b),
    .full(wfull)
    );
    
    //instantiate read domain comparator
    compare_rd cmp_rd(
    .rptr(rptr_b),
    .wptr(g2b_rd_op),
    .empty(rempty)
    );              
    
    
endmodule
 
module pointer
    #(
    parameter ADDR = 5  // parameterized size of pointers
    )
    (
    input wire clk,reset_b,op,fifo_status, // input-output declaration
      output reg [ADDR:0] gray,binary
     
    ); 
    integer i;
    
    always@(posedge clk, negedge reset_b)
        begin
        if(~reset_b)
            begin
            binary = 'd0;
            gray = 'd0;
            end 
        else if(op & ~fifo_status)
            binary <= binary + 1; 
        end
    
    always @(binary)
        begin
            gray[ADDR] = binary[ADDR];
            for (i=ADDR-1;i>=0;i=i-1)
    gray[i] = binary[i] ^ binary[i+1];
        end
        
endmodule   
 
module compare_wr
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire full
    );  
    //check for full condition: Write pointer has wrapped around but read pointer has not
    
        assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]);
endmodule 
 
module memory
    #(
    parameter DEPTH = 32, // parameter declaration
    WIDTH = 32,
    ADDR = 5
    )
    (
    input wire clk, reset_b, write, wfull, // input - output declaration
    input wire [ADDR-1:0] waddr, raddr,
    input wire [WIDTH-1:0] wdata,
    output wire [WIDTH-1:0] rdata
    );
    
    integer i;
    // creating memory
    reg [WIDTH-1:0] sram [DEPTH-1:0];
    
    // writing in the memory
    always @(posedge clk, negedge reset_b)
        begin
        if(~reset_b)
            begin
            for(i=0;i<DEPTH;i = i+1)
                sram[i] <= 'h0;
            end
        else if(write & ~wfull)
            sram[waddr] <= wdata;
        end 
    
    // reading a memory location
    assign rdata = sram[raddr];
endmodule
 
// to synchronize from fast clock domain to slow clock domain (write -> read)
module sync_w2r 
    #( 
    parameter ADDR = 5
    )
    (
    input wire clk, reset_b,
    input wire [ADDR:0] wptr,
    output reg [ADDR:0] wptr_rd
    );
    
    reg [ADDR:0] q;
    always @(posedge clk or negedge reset_b)
        begin
            if(~reset_b)
                begin
                    q <= 'd0;
                    wptr_rd <= 'd0;
                end
            else
                begin
                    q <= wptr;
                    wptr_rd <= q;
                end
        end
    
endmodule
 
// to synchronize from slow clock domain to fast clock domain (read -> write)
module sync_r2w
    #(
    parameter ADDR = 5
    )
    (
    input wire clk, reset_b,
    input wire [ADDR:0] rptr,
    output reg [ADDR:0] rptr_wr
    ); 
    
    reg [ADDR:0] q;
    always @(posedge clk or negedge reset_b)
        begin
            if(~reset_b)
                begin
                    q <= 'd0;
                    rptr_wr <= 'd0;
                end
            else
                begin
                    q <= rptr;
                    rptr_wr <= q;
                end
        end
endmodule
    
    
module compare_wr
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire full
    );  
    //check for full condition: Write pointer has wrapped around but read pointer has not
    
        assign full = (wptr[ADDR] != rptr[ADDR]) & (wptr[ADDR-1:0] == rptr[ADDR-1:0]);
endmodule 
 
module compare_rd
    #(
     parameter ADDR = 5 // declare parameter for memory address
    )                 
    (
    input wire [ADDR:0] rptr,wptr,  // declare inputs and outputs
    output wire empty
    );  
    //check for full condition: WRITE and READ pointers have NOT wrapped around
        
        assign  empty = wptr[ADDR:0] == rptr[ADDR:0];
endmodule
 
//TEST BENCH IS
`include "fifo_top.v"
`include "pointer.v"
`include "memory.v"    
`include "sync.v"
 `include "comparator.v"
module fifo_top_tb
 
reg write,wreset_b,wclk,read,rreset_b,rclk;
reg[31:0] wdata;
wire[31:0]rdata;
wire rempty,wfull;
  fifo_top ff(.write(write),.wreset_b(wreset_b),.wclk(wclk),.read(read),.rreset_b(rreset_b),.rclk(rclk),.wdata(wdata),.rdata(rdata),.rempty(rempty),.wfull(wfull));
 
  
  
  initial
    begin
      #5 @(posedge wclk or negedge wreset_b or negedge rreset_b)
   begin   write=1;
      wdata=0000001;
      #2wdata=00000010;
      #2wdata=00000011;
#1$display("rdata=%b,rempty=%b,wfull=%b",rdata,rempty,wfull);
     
      #2 read=1;
       #2wdata=00000100;
      #2wdata=00000101;
     #2 read=1;
  
        #1$display("rdata=%b,rempty=%b,wfull=%b",rdata,rempty,wfull);
      end 
      end  
        
      endmodule



ERRORS IS

Error-[SE] Syntax error
Following verilog source has syntax error :
"testbench.sv", 8: token is 'reg'
reg write,wreset_b,wclk,read,rreset_b,rclk;
^
 
Last edited by a moderator:

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,515
Helped
14,270
Reputation
28,805
Reaction score
12,973
Trophy points
1,393
Location
Bochum, Germany
Activity points
280,590
Review sv/verilog syntax rules, semicolon missing.
Code:
module fifo_top_tb[COLOR="#FF0000"];[/COLOR]
 

sai685

Junior Member level 2
Joined
Sep 4, 2015
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
292
yes, i have given it but after that when i am executing it is not displaying the output
 

sai685

Junior Member level 2
Joined
Sep 4, 2015
Messages
23
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
292
gif.PNG if you see here the code is executed but it is not displaying the ouptut.
 

ads-ee

Super Moderator
Staff member
Joined
Sep 10, 2013
Messages
7,826
Helped
1,811
Reputation
3,632
Reaction score
1,773
Trophy points
1,393
Location
USA
Activity points
59,095
Why do you expect the testbench to do anything?

Your testcase doesn't do anything, it just sits there with X's on every signal applied to the UUT.

Learn to write a working testbench with clocks and BFMs.

e.g. generating a testbench clock.

Code Verilog - [expand]
1
2
3
4
initial begin
  clk = 0;
  forever #5 clk = ~clk; // for a clock with a 10 time unit period
end

 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top