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asynchronous fifo design

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sumgupta89

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Hi frnds...i am working on "design and implementation of asynchronous fifo in VHDL" .i am just a beginer. I got a ready made code from asic-world.com. I got confused with some of the steps of that code.....can anyone please explain me what does those step means???????

1) whats the usage of presetfull and presetempty???
2) step no 117 -128 what does that mean ???????
3)step no 35 -39 ..how does the gray code conversion works in these steps???????

code ::

library ieee;
14 use ieee.std_logic_1164.all;
15 use ieee.std_logic_unsigned.all;
16
17 entity aFifo is
18 generic (
19 DATA_WIDTH :integer := 8;
20 ADDR_WIDTH :integer := 4
21 );
22 port (
23 -- Reading port.
24 Data_out :eek:ut std_logic_vector (DATA_WIDTH-1 downto 0);
25 Empty_out :eek:ut std_logic;
26 ReadEn_in :in std_logic;
27 RClk :in std_logic;
28 -- Writing port.
29 Data_in :in std_logic_vector (DATA_WIDTH-1 downto 0);
30 Full_out :eek:ut std_logic;
31 WriteEn_in :in std_logic;
32 WClk :in std_logic;
33
34 Clear_in:in std_logic
35 );
36 end entity;
37 architecture rtl of aFifo is
38 ----/Internal connections & variables------
39 constant FIFO_DEPTH :integer := 2**ADDR_WIDTH;
40
41 type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
42 signal Mem : RAM (0 to FIFO_DEPTH-1);
43
44 signal pNextWordToWrite :std_logic_vector (ADDR_WIDTH-1 downto 0);
45 signal pNextWordToRead :std_logic_vector (ADDR_WIDTH-1 downto 0);
46 signal EqualAddresses :std_logic;
47 signal NextWriteAddressEn :std_logic;
48 signal NextReadAddressEn :std_logic;
49 signal Set_Status :std_logic;
50 signal Rst_Status :std_logic;
51 signal Status :std_logic;
52 signal PresetFull :std_logic;
53 signal PresetEmpty :std_logic;
54 signal empty,full :std_logic;
55
56 component GrayCounter is
57 generic (
58 COUNTER_WIDTH :integer := 4
59 );
60 port (
61 GrayCount_out :eek:ut std_logic_vector (COUNTER_WIDTH-1 downto 0);
62 Enable_in :in std_logic; --Count enable.
63 Clear_in :in std_logic; --Count reset.
64 clk :in std_logic
65 );
66 end component;
67 begin
68
69 --------------Code--------------/
70 --Data ports logic:
71 --(Uses a dual-port RAM).
72 --'Data_out' logic:
73 process (RClk) begin
74 if (rising_edge(RClk)) then
75 if (ReadEn_in = '1' and empty = '0') then
76 Data_out <= Mem(conv_integer(pNextWordToRead));
77 end if;
78 end if;
79 end process;
80
81 --'Data_in' logic:
82 process (WClk) begin
83 if (rising_edge(WClk)) then
84 if (WriteEn_in = '1' and full = '0') then
85 Mem(conv_integer(pNextWordToWrite)) <= Data_in;
86 end if;
87 end if;
88 end process;
89
90 --Fifo addresses support logic:
91 --'Next Addresses' enable logic:
92 NextWriteAddressEn <= WriteEn_in and (not full);
93 NextReadAddressEn <= ReadEn_in and (not empty);
94
95 --Addreses (Gray counters) logic:
96 GrayCounter_pWr : GrayCounter
97 port map (
98 GrayCount_out => pNextWordToWrite,
99 Enable_in => NextWriteAddressEn,
100 Clear_in => Clear_in,
101 clk => WClk
102 );
103
104 GrayCounter_pRd : GrayCounter
105 port map (
106 GrayCount_out => pNextWordToRead,
107 Enable_in => NextReadAddressEn,
108 Clear_in => Clear_in,
109 clk => RClk
110 );
111
112 --'EqualAddresses' logic:
113 EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
114
115 --'Quadrant selectors' logic:
116 process (pNextWordToWrite, pNextWordToRead)
117 variable set_status_bit0 :std_logic;
118 variable set_status_bit1 :std_logic;
119 variable rst_status_bit0 :std_logic;
120 variable rst_status_bit1 :std_logic;
121 begin
122 set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor pNextWordToRead(ADDR_WIDTH-1);
123 set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor pNextWordToRead(ADDR_WIDTH-2);
124 Set_Status <= set_status_bit0 and set_status_bit1;
125
126 rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor pNextWordToRead(ADDR_WIDTH-1);
127 rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor pNextWordToRead(ADDR_WIDTH-2);
128 Rst_Status <= rst_status_bit0 and rst_status_bit1;
129 end process;
130
131 --'Status' latch logic:
132 process (Set_Status, Rst_Status, Clear_in) begin 133 if (Rst_Status = '1' or Clear_in = '1') then
134 Status <= '0'; --Going 'Empty'.
135 elsif (Set_Status = '1') then
136 Status <= '1'; --Going 'Full'.
137 end if;
138 end process;
139
140 --'Full_out' logic for the writing port:
141 PresetFull <= Status and EqualAddresses; --'Full' Fifo.
142
143 process (WClk, PresetFull) begin--D Flip-Flop w/ Asynchronous Preset.
144 if (PresetFull = '1') then
145 full <= '1';
146 elsif (rising_edge(WClk)) then
147 full <= '0';
148 end if;
149 end process;
150 Full_out <= full;
151
152 --'Empty_out' logic for the reading port:
153 PresetEmpty <= not Status and EqualAddresses; --'Empty' Fifo.
154
155 process (RClk, PresetEmpty) begin--D Flip-Flop w/ Asynchronous Preset.
156 if (PresetEmpty = '1') then
157 empty <= '1';
158 elsif (rising_edge(RClk)) then
159 empty <= '0';
160 end if;
161 end process;
162
163 Empty_out <= empty;
164 end architecture;


1 ----------------------------------------
2 -- Function : Code Gray counter.
3 -- Coder : Alex Claros F.
4 -- Date : 15/May/2005.
5 -- Translator : Alexander H Pham (VHDL)
6 ----------------------------------------
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.std_logic_unsigned.all;
10 use ieee.std_logic_arith.all;
11
12 entity GrayCounter is
13 generic (
14 COUNTER_WIDTH :integer := 4
15 );
16 port ( --'Gray' code count output.
17 GrayCount_out :eek:ut std_logic_vector (COUNTER_WIDTH-1 downto 0);
18 Enable_in :in std_logic; -- Count enable.
19 Clear_in :in std_logic; -- Count reset.
20 clk :in std_logic -- Input clock
21 );
22 end entity;
23
24 architecture rtl of GrayCounter is
25 signal BinaryCount :std_logic_vector (COUNTER_WIDTH-1 downto 0);
26 begin
27 process (clk) begin
28 if (rising_edge(clk)) then
29 if (Clear_in = '1') then
30 --Gray count begins @ '1' with
31 BinaryCount <= conv_std_logic_vector(1, COUNTER_WIDTH);
32 GrayCount_out <= (others=>'0');
33 -- first 'Enable_in'.
34 elsif (Enable_in = '1') then
35 BinaryCount <= BinaryCount + 1;
36 GrayCount_out <= (BinaryCount(COUNTER_WIDTH-1) &
37 BinaryCount(COUNTER_WIDTH-2 downto 0) xor
38 BinaryCount(COUNTER_WIDTH-1 downto 1));
39 end if;
40 end if;
41 end process;
42
43 end architecture;


reply plzzzzzzzzzzzzzzzzzzz
 

basicsofvlsi

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dude this is simple 32x8 fifo i think this will help u

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity fifo is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
enr: in STD_LOGIC;
enw: in STD_LOGIC;
datain: in STD_LOGIC_VECTOR (7 downto 0);
full: out STD_LOGIC;
empty: out STD_LOGIC;
dataout: out STD_LOGIC_VECTOR (7 downto 0)
);
end fifo;

--}} End of automatically maintained section

architecture fifo of fifo is
type datareg is array (0 to 31) of STD_LOGIC_VECTOR (7 downto 0);
signal memory:datareg:=(others=>(others=>'0'));
signal readptr,writeptr:STD_LOGIC_VECTOR (7 downto 0):="00000000";
begin


process(clk,rst)
begin
if(rst='0')then
writeptr<="00000000";
readptr<="00000000";
end if;
if(clk'event and clk='1' and enw='1')then
memory(conv_integer(writeptr))<=datain;
writeptr<=writeptr+'1';

end if;
if(writeptr="11111111")then
full<='1';
writeptr<="00000000";
else
full<='0';
end if;
if(writeptr<="00000000") then
empty<='1';
else
empty<='0';
end if;
if(clk'event and clk='1' and enr='1')then
dataout<=memory(conv_integer(readptr));
readptr<=readptr+'1';
end if;
if(readptr<="11111111")then
readptr<="00000000";
end if;
end process;
end fifo;
for further basic stuffs in vlsi check my blog https://basicsofvlsi.blogspot.com/
email:basicsofvlsi@gmail.com.
 

supercat

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I don't think there's any safe way to generate an immediate "full" output in the writer's clock domain except by synchronizing the read pointer into the writer's domain and comparing it to the write pointer there (causing a pessimistic buffer-full report); likewise with the "empty" output.

If the signal that would indicate the buffer has become full is gated with a signal which may asynchronously change and the resulting signal is used to preset a latch, such a signal may have runt pulses which could cause the latch to go directly into a metastable state.
 

sumgupta89

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thnx basicsofvlsi.....i hope it wd wrk :)
hv u worked with the asynchronous FIFO before????
 

permute

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well, the second example is a synchronous, not asynchronous.

For FPGAs, its much better to use the built in FIFOs, eg FIFO16, FIFO18, ect... for Xilinx parts.

otherwise you must add UCF constraints.

For async designs, setup/hold times can never be met. skew is also an issue. the result is that bit errors can be had on any transitioning bit.

gray code ensures that the other clock domain sees either N or N-1. for normal counter, the other clock domain might see N, N-1, N-2, N-3, N-4 ect... as multiple bits transition and thus multiple bits might miss setup/hold.

As mentioned, even with gray coding, skew is an issue. constraints must be in place to ensure the skew is less than one cycle.

I've never seen anyone write code like the second example. I'd try to stick with code that more closely matches the examples in the XST guide.
 

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