Asynchronous fifo design queries

[abhinavpr]

Hi,

I am new to logic design and trying to design an Asynchronous FIFO. can somebody suggest some good docs to read?
i came across a paper by cliff cummings on FIFO design which was very basic and well explained.

As it seems that paper is quite famous i would like to ask some question regarding the design in the paper or Async FIFO design in general as the design is very basic



1) In the design 2 FF synchronizer is used for both read pointer and write pointer . won't it depend on clock domain crossing?as from slow to fast CDC using a 2 FF synchronizer is fine but from fast to slow CDC the 2 FF design may not work. so should we be using different synchronizer at fast to slow CDC and slow to fast CDC.



2) Full and empty check : He has written that the updation would be immediate but i think differently,
assuming a situation where W_clk is faster than R_clk, two cases would arrive

a) when w_clk is marginally faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
and hence FIFO FULL would be asserted at FIFO depth -2.

b) when W_clk is much faster than the R_clk then the Rpointer value in the write pointer domain would arrive 2 rclk cycles later
and hence FIFO FULL would be asserted at FIFO depth - (some value).

in both the case the FIFO FULL detection is not immediate. and same goes for empty check condition too (applying different set of conditions).

plz enlighten me on the issue.

regards,

abhinavpr

 

[kuttu]

Hi Abhinav,

You can refer to this doccument

 

[qieda]

Hi,

regarding 1.)

2FF synchronizer are ok.
Because, if you go from fast to slow clock. You will not get every pointer value on the slow side. But due to the gray coding you will always have a stable value. With this the remaining logic is ok and stable.

Regarding 2.) You are right. The full or early detection may be to late or early. But it is always on the save side. E.g. looking at full. This is detected on the write side. You get a synchronized read pointer. This is either the correct pointer, or it shows the status of some cycles before. So you may detect a full scenario, but your fifo isn't full anymore. But you will never write into a full fifo. You will only stop your pipeline, when it isn't needed.


regards

 

[jsherman]

I found this book to be useful in reading about asynchronous circuit design:

**broken link removed**