Asynchronous Design, simulation, synthesis and power tools

[negreponte]

Could you inform me pls?

thank you

 

[arunragavan]

Re: Asynchronous Design, simulation, synthesis and power too

There is one wonderful book

Asynchronous design by Chris J.Myres published my John Willy and Sons.

I have the entire book.. i shall upload the book if u need them.. its around 40MB with all details.

with regards,

 

[sarath51]

Re: Asynchronous Design, simulation, synthesis and power too

**broken link removed**
check this site as well . This has quite a few interesting books on design

 

[xiongdh]

Re: Asynchronous Design, simulation, synthesis and power too

the URL can't be connect.

The requested URL could not be retrieved

 

[negreponte]

arunragavan,
could you upload, this book pls?
thank you

 

[vibhute_r_p]

Hey you will get some good info in follwoing book -
There is a full set aviliable for async design. serach for BALSA
**broken link removed**

for book -

 

[gaonkc]

you can see <<Asynchronous circuit design>>

 

[arunragavan]

Re: Asynchronous Design, simulation, synthesis and power too

Details about the Book

Asynchronous Circuit Design. Chris J. Myers
Copyright  2001 by John Wiley & Sons, Inc.
ISBNs: 0-471-41543-X (Hardback); 0-471-22414-6 (Electronic)

Asynchronous Ciruit Design

A Wilcplnterscience Publication
JOHN WILEY 8z SONS, INC.
New York / Chichester / Weinheim / Brisbane / Singapore / Toronto


Contents of the Book


Preface
Acknowledgments
I Introduction 1
I. 1 Problem Specification 1
1.2 Communication Channels 2
1.3 Communication Protocols 4
1 .,J Graphical Representations 8
1.5 Delay-Insensitive Circuits 10
1.6 Hujjfman Circuits 13
I. 7 Muller Circuits 16
1.8 Timed Circuits 17
1.9 Verification 20
1.10 Applications 20
1.11 Let’s Get Started 21
1.12 Sources 21
Problems

2 Communication Channels 23
2.1 Basic Structure 24
2.2 Structural Modeling in VHDL 27
2.3 Control Structures 31
2.3.1 Selection 31
2.3.2 Repetition 32
2.4 Deadlock 34
2.5 Probe 35
2.6 Parallel Communication 35
2.7 Example: MiniMIPS 36
2.7.1 VHDL Specification 38
2.7.2 Op timixed MiniMIPS 48
2.8 Sources 52
Problems

3 Communication Protocols 57
3.1 Basic Structure 57
3.2 Active and Passive Ports 61
3.3 Handshaking Expansion 61
3.4 Reshufling 65
3.5 State Variable Insertion 66
3.6 Data Encoding 67
3.7 Example: Two Wine Shops 71
3.8 Syntax-Directed Translation 73
3.9 Sources 80
Problems

4 Graphical Representations
4.1 Graph Basics
4.2 Asynchronous Finite State Machines
42.1 Finite State Machines and Flow Tables
42.2 Burst-Mode State Machines
4.2.3 Extended Burst-Mode State Machines
4.3 Petri Nets
43.1 Ordinary Petri Nets
4.3.2 Signal Transition Graphs
Timed Event/Level Structures
4.5 Sources
Problems

5 Hunman Circuits
5.1 Solving Covering Problems
5.1.1 Matrix Reduction Techniques
5.1.2 Bounding
5.1.3 Termination
5.1 .d Branching
5.2 State Minimization
5.2.1 Finding the Compatible Pairs
5.2.2 Finding the Maximal Compatibles
5.2.3 Finding the Prime Compatibles
5.2.4 Setting Up the Covering Problem
5.2.5 Forming the Reduced Flow Table
5.3 State Assignment
5.3.1 Partition Theory and State Assignment
5.3.2 Matrix Reduction Method
5.3.3 Finding the Maximal Intersectibles
5.34 Setting Up the Covering Problem
5.3.5 Fed-Back Outputs as State Variables
5.4 Hazard-Free Two-Level Logic Synthesis
54.1 Two-Level Logic Minimization
5.4.2 Prime Implicant Generation
54.3 Prime Implicant Selection
5.4 4 Combinational Hazards
5.5 Extensions for MIC Operation
5.5.1 Transition Cubes
5.5.2 Function Hazards
5.5.3 Combinational Hazards
5.54 Burst-Mode Transitions
5.5.5 Extended Burst-Mode Transitions
5.5.6 State Minimization
5.5.7 State Assignment
5.5.8 Hazard-Free Two-Level Logic Synthesis
5.6 Multilevel Logic Synthesis
5.7 Technology Mapping
5.8 Generalized C-Element Implementation
5.9 Sequential Hazards
5.10 Sources
Problems

Muller Circuits 207
6.1 Formal Definition of Speed Independence 208
61.1 Subclasses of Speed-Independent Circuits 210
6.1.2 Some Useful Definitions 212
6.2 Complete State Coding 216
6.2.1 Transition Points and Insertion Points 217
6.2.2 State Graph Coloring 219
6.2.3 Insertion Point Cost Function 220
6.2.4 State Signal Insertion 222
6.2.5 Algorithm for Solving CSC Violations 223
6.3 Hazard- Free Logic Synthesis 223
6.3.1 Atomic Gate Implementation 225
6.3.2 Generalized C-Element Implementation 226
6.3.3 Standard C-Implementation 230
6.3.4 The Single- Cube Algorithm 238
6.4 . Hazard-Free Decomposition 243
6.4.1 Insertion Points Revisited 245
6.4.2 Algorithm for Hazard-Free Decomposition 246
6.5 Limitations of Speed-Independent Design 248
6.6 Sources 249
Problems 251

7 Timed Circuits 259
7.1 Modeling Timing 260
7.2 Regions 262
7.3 Discrete time 265
7.4 Zones 267
7.5 POSET Timing 280
7.6 Timed Circuits 289
7.7 Sources 292
Problems 293

8 Verification 295
8.1 Protocol Verification 296
8.1.1 Linear- Time Temporal Logic 296
8.1.2 Time- Quantified Requirements 300
8.2 Circuit Verification 303
8.2.1 Trace Structures 303
8.2.2 Composition 305
8.2.3 Canonical Trace Structures 308
8.2.4 Mirrors and Verification 310
8.2.5 Strong Conformance 312
8.2.6 Timed Trace Theory 314
8.3 Sources 315
Problems 316

9 Applications
9.1 Brief History of Asynchronous Circuit Design
9.2 An Asynchronous Instruction-Length Decoder
9.3 Performance Analysis
Testing Asynchronous Circuits
The Synchronization Problem
9.5.1 Probability of Synchronixation Failure
9.5.2 Reducing the Probability of Failure
9.5.3 Eliminating the Probability of Failure
95.4 Arbitration
9.6 The Future of Asynchronous Circuit Design
9.7 Sources
Problems

Appendix A VHDL Packages
A. 1 nondeterminism.vhd
A.2 channel.vhd
A.3 handshake.vhd
Appendix B Sets and Relations 359
B.i Basic Set Theory 360
B.2 Relations 362
References 365

 

[AlexWan]

Hi all,

The PDF from following links can't be opened. Can anyone upload it again?

h**p://

 

[arunragavan]

Re: Asynchronous Design, simulation, synthesis and power too

The rest of the Files

 

[howz]

this is a good book...it help me a lot..
thank you for being so kind and hellpful

 

[Thomson]

Re: Asynchronous Design, simulation, synthesis and power too

Hi all,

The PDF from following links can't be opened. Can anyone upload it again?

h**p://

 

[Thomson]

Re: Asynchronous Design, simulation, synthesis and power too

Hi,
although i'm currently reading the book pasted by myself due to one occasional opportunity when i wanted to summarize the topic about asynchronous signals transferring amongst the different clock domain, i really have no such intention to study this enormous field.

Basically i've not encountered so many logics implemented by asynchronous ways, which confused me a lot whether i shall study them by paying a lot of time.

In addition, i'm not familiar with such circuits including their performance,implementing ways and the testing and verification methods. So i really appreciate your advice and knowledge shared with me if you've designed such circuits and really feel that it's a tendancy in the long run of the ASIC design.

Thansk,

Thomson