Asynchronous asymmmetric FIFO in VHDL

[umair.razzaq]

Hi all,

I have designed an Asynchrounous asymmetric fifo using VHDL constructs.It is generic fifo with depth and prog_full as generics. It has 32-bit in 16-bit output data width.
You can find the fifo design here.
The top level fifo (fifo_wrapper.vhd) is built upon an asynchronous 32-bit fifo(async_fifo.vhd). This internal fifo (async_fifo) is build using the logic from generic FIFO on
open cores (https://opencores.org/project,generic_fifos). I have added a simple testbench to try out this fifo design.
BUT there is some issue with this design that I am not able to figure out. The fifo design works perfectly fine when I simulate it, but when I synthesize it and run It along with
my other design on hardware I get some erroneous data sometimes. May be there is some corner case that I am not able to simulate or Is it some thing else?

That's why I would like anyone who needs this design to try it and let me know if he/she encounters any Issues during simulation or after synthesis.
If you need further info mail me at umair[dot]razzaq[at]gmail com

thanks
Umair
PS: kindly let me know if there is some other forum where I can put my design for public use. thanks

 

[TrickyDicky]

Hi

Well done on this, but why would anyone chose your async fifo over the ones created by altera and xilinx that you can use for free already?

And it doesnt inspire me with confidence when you have conflicting libraries in your async_fifo.vhd and testbench files.

 

[umair.razzaq]

Hi

Well done on this, but why would anyone chose your async fifo over the ones created by altera and xilinx that you can use for free already?

Thank you, and the main motivation behind doing it was that this fifo is a part of big project under development on which multiple engineers are working. Each has to regenerate fifo everytime from xilinx cores and it was problematic sometimes. So I thought of making a fifo from VHDL constructs. although I found asynchrounous fifo but there is none which is both asynchronous and assymetric. I hope others will find this useful too .

And it doesnt inspire me with confidence when you have conflicting libraries in your async_fifo.vhd and testbench files.

I can't figure out what are pointing to (I am using the same libraries in both files). Nevertheless, I would like to know, does it make any difference what libraries am I using in testbench.

 

[TrickyDicky]

std_logic_arith and numeric_std have conflicts. Add to this the fact that std_logic_arith is not a VHDL standard library, you should stop using std_logic_arith.

As for engineers having to regenerate fifos - yes, that happens, but you dont need to use coregen, you can instantiate them yourself using generics. But if you want effecient implementation, coregen is going to be the only way to go (especially if you want to use the hard fifo modes of the BRAMs).

 

[umair.razzaq]

Thanks alot for the advice on libraries

As for instantiating cores using generics, I tried to use instantiation template from xilinx for asymmetric RAM (Language templates:VHDL --> Synthesis Constructs --> Coding Examples --> RAM --> Block RAM --> Dual Port --> Asymmetric Ports--> Read-First ).
But this did not synthesis as it is using a 'for loop' . I did not find any other thing close to async and asymm fifo. Any Ideas for instantiating it via generics??

 

[jrwebsterco]

A couple of quick comments on what I've read here ...

First, I agree you should try to use COREGEN.
I'm personally not familiar with instantiation using generics for synthesis (though I think this does occur inside the instantiation "wrapper" out of COREGEN, so that simulation uses the common FIFO behavioral model instead of the primitives netlist from COREGEN).

Note that you can batch COREGEN to modify FIFO params and regen, if this helps with your original concern with COREGEN.
Go to Xilinx support and search for "coregen command" and you'll find some leads on how to do this.
Note that the response to the one titled "Coregen, command line usage" lists some good caveats to be aware of.

BTW, those ISE Language Templates are really just helpful code-snippets (and not complete IP) for common types of RTL operations/functions.
Instead, a FIFO is a higher-level system of multiple functions (e.g. a 2-port RAM *plus* a controller).

Finally, FWIW, regarding why you were running into erroneous data with your original RTL implementation ...
You appear to have used the NON-grey-coded version of the OpenCores FIFO design (i.e. the pointers are incremented linearly/binarily and not as a Grey code).
Because of this, you are likely running into fundamental CDC issues when re-sampling the write/read pointers across to the other clock.
If you must pursue your own RTL approach, I'd also suggest scanning through the following papers ...
-> http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
-> http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf