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Reset can be either Active high or Low. That depends on the target device logic. There are active high reset devices available (example : **broken link removed**). But the reason for resets to be active low is because RESET is intended to keep all devices in sleep-mode (reset mode) when power rails are coming up slowly. So if you have an active high reset, the reset signal itself might have not come up to proper voltage levels and it may not properly reset the target device. Also please keep in mind Active high ot low resets will have no effect on power drawn by CMOS. Yes, on TTL it will have some difference.
And... that's the same reason why reset signals are independent of any other logic, hence asynchronous. But at the same time they can be made synchronous too ;-).. see below:
module sync_rst (clk,rst);
always @ (posedge clk )
if ( rst == 1'b1) begin
---------- Post added at 07:18 ---------- Previous post was at 07:13 ----------
Also please have a look at this notes : **broken link removed**