maulin sheth
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Hello All,
How to find the asynchronous reset is active high or active low in the design using Design Compiler?
As Top level reset port is connected through inverter to some sequential logic and sometimes it is connected through non inverted...so how to find this...specifically in DC.
Thanks & Regards,
Maulin Sheth
How to find the asynchronous reset is active high or active low in the design using Design Compiler?
As Top level reset port is connected through inverter to some sequential logic and sometimes it is connected through non inverted...so how to find this...specifically in DC.
Thanks & Regards,
Maulin Sheth