Association of Verilog module and VHDL component declaration in Conformal LEC

[Manoj Kumar S]

I am working on verifying the equivalence of an RTL design and netlist using Conformal LEC. A few verilog modules have their corresponding component declaration in VHDL. I have read the verilog designs with the option -noelaborate, but still these modules and components don't get associated and the components are blackboxed. Can anyone help me with this issue?

Thanks in advance
Manoj Kumar

 

[ro9ty]

Couple of things you need to check.
First make sure that the translation is not off.
For LEC it is pertinent to read the file with the component declaration. Hence, you need to read the verilog files before the VHDL where you are instantiating it. Also, make sure that you read all of them together since you are not elaborating the design like this read design - noelab -verilog xyz.v \
-vhdl xxz.vhd.

This should resolve the issue.

Ro9ty

 

[pdude]

why use elaboration separately ??