Assignments in an always block

[kingslayer]

Dear all,

I once read somewhere that it is good design rule to have only one signal assigned in a process in Verilog. That is, if we have three signals, it is better to have three processes instead of a single one. I am now wondering... why? Do you have any idea on the applicability of this rule? What about complex designs?

Thanks in advance
Cheers

 

[mail4idle2]

It is only from the readability perspective.

 

[dave_59]

I've never heard that rule. You are very likely to have to repeat the same expressions in the three separate processes creating more opportunity for mistakes.

I think someone may have confused the synthesis rule that says you can only assign variable from a single process, and not multiple assignments to the same signal from multiple processes.