Assigning values to an array in Verilog

[bcdeforest]

I have an output "SUM". I need to assign 4 values into its array. Here is my attempt.

module part4b(A,B,Cin,S,Cout,SUM,V);
input [3:0]A,B;
input [1:0]S;
input Cin;
output [3:0]SUM;
output Cout,V;
reg [3:0]SUM;
reg Cout,V;
wire w1,w2,x1,x2,y1,y2,z1,z2;//Connecting wires to module
 
part4a a0(.A(A[0]),.B(B[0]),.Cin(Cin),.S(S),.SUM(w1),.Cout(w2));//Wire w2 connects a0 and a1 C
part4a a1(.A(A[1]),.B(B[1]),.Cin(w2),.S(S),.SUM(x1),.Cout(x2));//Wire x2 connects a1 and a2 C
part4a a2(.A(A[2]),.B(B[2]),.Cin(x2),.S(S),.SUM(y1),.Cout(y2));//Wire y2 connects a2 and a3 C
part4a a3(.A(A[3]),.B(B[3]),.Cin(y2),.S(S),.SUM(z1),.Cout(z2));//Wire w2 is output Cout
assign SUM[0] = w1;//THESE RIGHT HERE<<
assign SUM[1] = x1;
assign SUM[2] = y1;
assign SUM[3] = z1;
endmodule

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The error I get is, "Object "SUM" on left-hand side of assignment must have an net type"

 

[ads_ee]

assign can not be performed on a variable of type reg.
1. change the declaration of reg [3:0] SUM; to wire [3:0] SUM;
2. remove the reg declaration of SUM entirely as it's already declared by output [3:0] SUM;

Regards,
-alan

 

[dave_59]

BTW, you are using a very old style of Verilog port declarations where you list the identifiers twice or even three times if you need to declare an output as reg. You should use this:

module part4b(
input [3:0]A,B,
input Cin,
input [1:0]S,
output reg Cout,
output [3:0]SUM,
output reg V
);

Any port declared without a data type is implicitly a wire.