Code VHDL - [expand] 1 type instr is (alu_add, alu_sub, alu_and, alu_or, alu_xor, alu_nor);
Code VHDL - [expand] 1 instr_str := "or";
Since you've defined 'instr_str' to be a four character string, you can't assign just three characters to it as you're doing in almost all of your assignments.String in VHDL is declared as a character array. Thus, in my case I have declared a string that can contain the largest string assigned to it in a select case construct:
So I have: variable instr_str : string (1 to 4); and then assigning value to it in case statement.
case instr(5 downto 0) is
when alu_add =>
instr_str := "add";
when alu_sub =>
instr_str := "sub";
when alu_and =>
instr_str := "and";
when alu_or =>
instr_str := "or";
when alu_xor =>
instr_str := "xor";
when alu_nor =>
instr_str := "nor";
when others =>
end case;
function to_string(Instr: t_INST_TYPE) return String is
begin
case Instr is
when alu_add => return("add");
when alu_sub => return("sub");
when alu_and => return("and");
when alu_or => return("or");
when alu_xor => return("xor");
when alu_nor => return("nor");
when others => return("");
end case;
end function to_string;
The short answer is because the language does not allow you to do this.Why can't I just declare a string in VHDL and then assign variable length strings to it as long as they are not bigger than the upper bound of the string declaraction?
OK, this does solve my problem. I have realized my folly. At present this is what I have and it must now be changed into an enumerated type
function From_String(S: String(5 downto 0)) return t_INST_TYPE is
begin
case S is
when "100000" => return(alu_add);
when "100010" => return(alu_sub);
when "100100" => return(alu_and);
when "100101" => return(alu_or);
when "100110" => return(alu_xor);
when "100111" => return(alu_nor);
when others => report "Unexpected instruction " & image(S) severity ERROR; return([COLOR=#FF0000]alu_add[/COLOR]); -- Still need to return 'something' after the assertion
end case;
end function From_String;
Personally, I wouldn't use attributes, what I would do is define a 'to_unsigned' function (or 'to_std_ulogic_vector') that converts the enum into an unsigned or a std_ulogic_vector. Then to print it out you can use image() or heximage(). The reason for preferring the two step is that the 'to_unsigned' and 'to_std_ulogic_vector' functions will typically have usages outside of just converting them into a printable string.This is what I have in the architecture of the testbench
type opcode is (alu_add, alu_sub, alu_and, alu_or, alu_xor, alu_nor);
attribute opcode_encoding : string;
attribute opcode_encoding of opcode: type is "100000 100010 100100 100101 100110 100111";
Having applied the encoding. How can I print the encoded value? e.g if I set
variable myopcode : opcode := alu_sub;
Now how do I print the encoded value of myopcode which is "100010" in this case?
function to_std_ulogic_vector(L: t_INST_TYPE ) return std_ulogic_vector is
variable RetVal: std_ulogic_vector(5 downto 0);
begin
case L is
when alu_add => RetVal := "100000";
when alu_sub => RetVal := "100010";
when alu_and => RetVal := "100100";
when alu_or => RetVal := "100101";
when alu_xor => RetVal := "100110";
when alu_nor => RetVal := "100111";
end case;
return(RetVal);
end function to_std_ulogic_vector;
See #11I'd be keen to see an answer to #8.
Displayed where? You can convert it into a printable string, but you can't 'display' the attribute in a waveform window if that's your question. However, in your waveform window Modelsim will already display 'opcode' as the enumeration (i.e. 'alu_add', alu_xor', etc.) which is far better than displaying the hex or binary counterpart.It'd be nice to see the bit vector being displayed when you specify a type.
See post #11I know attribute opcode_encoding of opcode: type is "100000 100010 100100 100101 100110 100111"; is used for FSM see https://www.doulos.com/knowhow/fpga/fsm_optimization/
However...how to do you then print the string? Can modelsim handle this?
Code:x <= alu_xor; wait for 1 ns; write(line, opcode'image(x)) -- ...just prints the text of what state it's in. (alu_xor)
write(line, heximage(to_std_ulogic_vector(opcode))); -- I have 'image' and 'heximage' functions in a library of commonly used 'stuff'
But 100110 is not the 'value' of opcode, it is just an attribute of opcode. The 'value' is 'alu_xor'.How to get 'val or value which should be 100110
hwrite(line, to_std_ulogic_vector(opcode));
write(l, "you can do this (" & heximage(to_std_logic_vector(opcode)) & ") in 1 line of code" & LF);
--instead of
write(l, string'("you can do this(") );
hwrite(l, to_std_ulogic_vector(opcode));
write(l, string'(") in 3 lines of code"));
write(l, "" & "This is a string");
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