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Assigning Value for Logic 1 in Verilog testbench

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aarthy_maya

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Hi,

I am newbie to Verilog.
I am trying to write a test-bench for my custom design circuits using Verilog. The Simulation is done in Cadence ADE using AMS simulator. The problem is, the PDK uses two different voltages (1.8/3.3V), so when I run the simulation, the Value of logic 1 is at 1.8V. I have defined VDD as global pin with value equal to 3.3V. But it doesn't help :-(

Can anyone help to solve it? where I am wrong. And what I should do to get the value to logic 1 value to be 3.3V

Thanks!
Aarthy
 

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