assign inout wire (verilog)

module t5(Addr, IO, Clk, RWL, ResetL);
	input	[2:0] Addr;
	input	Clk, RWL, ResetL;
	inout	[7:0] IO;
	
	reg	[7:0] r [7:0];
	integer	i;
	
	always @(posedge Clk or negedge ResetL)
		if (!ResetL) begin
			for (i = 0; i < 8; i=i+1)
				r[i] <= 0;
		end
		else	begin
			if (!RWL)
				r [Addr] <= IO;
		end
		
		assign IO = (!RWL) ? 8'bz : r[Addr];
		
endmodule

module tt5;

	// Inputs
	reg [2:0] Addr;
	reg Clk;
	reg RWL;
	reg ResetL;

	// Bidirs
	wire [7:0] IO;

	// Instantiate the Unit Under Test (UUT)
	t5 uut (
		.Addr(Addr), 
		.IO(IO), 
		.Clk(Clk), 
		.RWL(RWL), 
		.ResetL(ResetL)
	);

	initial begin
		// Initialize Inputs
		Addr = 0;
		Clk = 0;
		RWL = 0;
		ResetL = 0;

		// Wait 100 ns for global reset to finish
		#100;
		ResetL = 1;
		Addr = 1;
		IO = 10;
		#50;
		Clk = 1;
		#50;
		Clk = 0;
		RWL = 1;
		
		
		// Add stimulus here

	end
      
endmodule

wire [10:0] IO;
reg [10:0] IOreg;

assign IO = IOreg;

initial
  begin
    IOreg = some value;
    #(some time) IOreg = some value;
    #(some time) IOreg = {10{1'bz}};             // tristate
  end