assign a value to output

[appu1985]

I have this code i just want the output of pim to be any integer value after 100s what should be done..
The value in t should be assinged to pim which is displayed on the waveform irrespective of the inputs

module wave(mode,p,x,clk,pim);
input [1:0]mode;
input [3:0]p;
input [7:0]x;
input clk;
output [3:0]pim;
wire [3:0]t;

initial 
begin
t = 4'b0110;
end
 
 assign pim = t;
endmodule

actually pim should be assigne the value of t..pls chk it nd correct it

 

[echo47]

Hi,
Verilog doesn't allow initializing a wire (t) with a value (4'b0110).
Maybe you meant t to be a register?

I don't understand the words "any integer value after 100s".

 

[appu1985]

ok if u do it a register and i want that register value to be in pim after a delay of 100 what does the code look like,

 

[echo47]

What are the units on "100"? Earlier you mentioned "100s", so do you mean "100 seconds", or something else?

Your delay-to-pim description is not clear to me. Are you trying to build a 100 second delay line? That could require a huge amount of memory, depending on your clock rate. Or do you simply want to wait 100 seconds after FPGA startup, and then write one value into pim? That would be a simple counter, depending on your clock rate.