Assertion

Hi all.

Iam writting system verilog Assertion, i have come across with a problem in below code

$rose (req) |-> ##delay $rose (ack);
in tha above code variable delay i want to be chaging based on contents of some register, but am getting error : delay should be constant ---i tried passing delay through generate construct, since my register is 16 bit i have to generate 65535 gen blocks so its giving memory related issue,whts the solution??????

you can't set the "delay" as a veriable.
it must be a constant or a range.

can u tell me how to learn system verilog assertions pls .

@(posedge clk)(($rose(A),count=0) |-> (1, count++)[*0:MAX_COUNT] ##1 (B and count == m));

Variable delay is supported as long as you know the MAX_COUNT

use it:
$rose (req) ||-> ##delay $rose (ack);