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Assertion based verification

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karthikeyan

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What u mean by Assertion Based Verification and usages? and what is different b/w 0-IN & OVL Assertions?

Is it possible to see a assertion coverages??

clarify the doubts to me.......

Thanx in advance
 

zhangpengyu

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Hi
I think assertion verification is insert event in hdl code,then tools can collect the information from the code.
zhpy
 

AlexWan

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pls reference:

hxxp://www.verificationlib.org

good luck!
 

xworld2008

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when you do verification, you can use assert to warn the data have error, this can reduce you
debug time.
 

karthikeyan

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Is it possible to see a Assertion Coverages???
 

AlexWan

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karthikeyan said:
Is it possible to see a Assertion Coverages???
I think we get the coverage of assertion with the assertion report.
During verification with assertion, the assertion function is used by normal RTL code. If the assertion is executed, the coverage rate will be counted.
 

AlexWan

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karthikeyan said:
Is it possible to see a Assertion Coverages???

Certainly, I think we don't need the assertion coverage.
For this, we may use the asseration in the testbench, not RTL code. With the hierachical calling, we call the assertion module in the TB.
Other way, use assertion with the specified comments by simulation tools. During verification, the coverage tool will dont counte the hit rate of assertion statements.

Good luck
 

karthikeyan

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What is different between OVL,OVA and 0IN based assertions?
 

AlexWan

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karthikeyan said:
What is different between OVL,OVA and 0IN based assertions?
Sorry!
Can you spell the OVA and OIN?
I only know about and use the OVL.
 

karthikeyan

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OVA : Open Vera Assertions(synopsys)
0(zero)IN: company name.,0IN based Assertion Based verification.
 

vale

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karthikeyan said:
OVA : Open Vera Assertions(synopsys)
0(zero)IN: company name.,0IN based Assertion Based verification.
It seems that synopsys is pushing up systemverilog to substitute "verilog + vera" in future. The assertion based verification is one of the key features of SV. IMHO, ABV is an useful method to aid verification, but it can't solve all problems.
 

nagraj

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AlexWan said:
karthikeyan said:
Is it possible to see a Assertion Coverages???

Yes, The tools nowadays support assertion based coverage reports which will give information regarding number of assertion being fired ..etc.

Certainly, I think we don't need the assertion coverage.
For this, we may use the asseration in the testbench, not RTL code. With the hierachical calling, we call the assertion module in the TB.
Other way, use assertion with the specified comments by simulation tools. During verification, the coverage tool will dont counte the hit rate of assertion statements.

Good luck
 

AH Ling

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ABV is an verification methodology that can be classified into three approaches:

1. functional coverage: this is not code coverage but it is to verify completeness of you test against specification. if you get 100%, means all your function are met according to your spec.

2. constrained-random test: constrained test is to simulate specific scenario and random here refer to randomize your inputs to expose corner cases

3. coverage-driven verification: combines both 2 aprroaches above...to eliminate repetitive test of same scenario that is correct...

System verilog is the HDL that could support ABV....
 

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