ravikanth_bvrkc
Junior Member level 3
Hello Guys
I need help on assertion and deassertions in Timing diagrams which are further used in state machines and ASM charts in implementing FPGAs. To be precise, how are SB, SE, DSE and DSB assigned? Thanks in advance.
I need help on assertion and deassertions in Timing diagrams which are further used in state machines and ASM charts in implementing FPGAs. To be precise, how are SB, SE, DSE and DSB assigned? Thanks in advance.