ask for help on self_checking testbench

[asing123]

I am now learning writing self_checking testbench.I can verify the outputs directly controlled by inputs.but I don't know how to write those testbenches whose outputs are controlled not directly by inputs but by internal signals.such as a simple divider,Would you give me some good advice? in additon,I hope to get more advice except those which can only be used by the divider,because what I will verify is more complex than the divider. thank you.

module divider(q , rst ,cp);
output q;
input rst,cp;
reg [1:0] counter;

assign q=(counter==2)?1'b1:1'b0;

always @(posedge cp)
begin
if (rst)
counter<=0;
else
if (counter==3)
counter<=0;
else
counter<=counter+1;
end

endmodule

 

[Bartart]

Hi!


you can find a tutorial on self_checking testbench

@ **broken link removed**

or https://www.xilinx.com/bvdocs/appnotes/xapp199.pdf


good luck!

bart

 

[asing123]

Bartart,thank for your enthusiasm,but it seems that examples provided there are the same as I wrote above ,that is ,their outputs are controlled directly by inputs ,not by internal signals.would you give me some other advice?thanks.