[SOLVED] ask example to simulate with QUARTUS II v11.1 web edition and modelsim-altera

[joseMiguel]

Hi,

I wrote a simple counter with a testbench and try to simulate it with modelsim-altera.
i got the signals of the counter on modelsim-altera but there are undriven.
remark: the project has the name of the top entity.

coud you help me please.
JoseMiguel

 

[vipinlal]

make sure that the signal in initialized to zero..otherwise they will appear as "U" in simulation..

if it still doesnt work, pls post your code hear.

 

[joseMiguel]

hi,

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity counterModulo16 is port(
    CLK, nRST: in std_logic;
    Q           : out unsigned(7 downto 0));
end counterModulo16;
 
architecture archCounterModulo16 of counterModulo16 is 
signal TEMP: unsigned(Q'range);
begin
    process(CLK, nRST) begin
        if (nRST='0') then 
            TEMP <= (others=>'0');
        elsif (CLK'event and CLK='1') then 
            TEMP <= TEMP + 1;
        end if;
    end process;
    
    Q<= TEMP;
end archCounterModulo16;

---

and the testbench:

---

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb_counter16 is
end entity  tb_counter16;
 
architecture archtb_counter16 of tb_counter16 is 
signal sCLK: std_logic;
signal snRST: std_logic;
signal sQ: unsigned(7 downto 0);
 
begin
dut: entity work.counterModulo16
    
    
    port map(sCLK,
                snRST,
                sQ);
                
    snRST <= '0' , '1' after 2 ns;
    
    sCLK <= not sCLK after 4 ns;
    
end archtb_counter16;

---

thank you
JoseMiguel

 

[vipinlal]

signal TEMP: unsigned(Q'range) := (others => '0');

try changing it like this..

 

[joseMiguel]

Hi

it seems that it does not take in account the testbench.
Q and TEMP are 0000000 but there are no countering.
remark: the name of the project is counterModulo16.

Thank you
JoseMiguel

 

[TrickyDicky]

are you sure you're simulating the testbench and not counterModulo16?

 

[joseMiguel]

Hi,

i did an another project with the testbench as top entity and small modifications.
i have an error:
error (12060): can't synthesize current design -- design does not contain any logic

1) the testbench
code VHDL - [expand]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.counter16_pkg.all;

entity tb_counter16 is
end entity  tb_counter16;

architecture archtb_counter16 of tb_counter16 is 
signal sCLK: std_logic;
signal snRST: std_logic;
signal sQ: unsigned(7 downto 0);

begin
dut: counter16
	
	port map(sCLK,
				snRST,
				sQ);
				
	snRST <= '0' , '1' after 2 ns;
	
	sCLK <= not sCLK after 4 ns;
	
end archtb_counter16;

2) the counter
code VHDL - [expand]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity counter16 is port(
	CLK, nRST: in std_logic;
	Q			: out unsigned(7 downto 0));
end counter16;

architecture archCounter16 of counter16 is 
signal TEMP: unsigned(Q'range);
begin
	process(CLK, nRST) begin
		if (nRST='0') then 
			TEMP <= (others=>'0');
		elsif (CLK'event and CLK='1') then 
			TEMP <= TEMP + 1;
		end if;
	end process;
	
	Q<= TEMP;
end archCounter16;

3) the package
code VHDL - [expand]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package counter16_pkg is

component counter16 port
(CLK, nRST: in std_logic;
	Q			: out unsigned(7 downto 0));
end component;

end counter16_pkg;

thank you
JoseMiguel

 

[raystings]

Hi Jose Miguel,

you don't need a package. Just remove it and take the counter module for synthesis.

In your current design the compiler can't find anything, because nothing is instantiated in your package. Instead of a package you can use a top module or a wrapper

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity top_counter is port(
    CLK, nRST: in std_logic;
    Q           : out unsigned(7 downto 0));
end top_counter;
 
component counter16 port
(CLK, nRST: in std_logic;
	Q			: out unsigned(7 downto 0));
end component;

 
architecture arch of top_counter is 
begin

inst_counter16 : counter16 
port map
(  CLK   => CLK,
   nRST => nRST,
   Q	   => Q
);   

end arch;

 

[joseMiguel]

Hi,

i still have an error:
error(12060): can't synthesize current design - design does not contain any logic

Could someone try this example and send to me the solution.
with the name of the project and all the files of the project.

thank you
Jose Miguel

 

[vipinlal]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity counter16 is port(
	CLK, nRST: in std_logic;
	Q			: out unsigned(7 downto 0));
end counter16;

architecture archCounter16 of counter16 is 
signal TEMP: unsigned(Q'range);
begin
	process(CLK, nRST) begin
		if (nRST='0') then 
			TEMP <= (others=>'0');
		elsif (CLK'event and CLK='1') then 
			TEMP <= TEMP + 1;
		end if;
	end process;
	
	Q<= TEMP;
end archCounter16;

Use the counter16 code alone for synthesis. Remove all other codes from project.

 

[joseMiguel]

Hi,

This code could be synthesize but for simulation, how can i do???

thank you.
Jose Miguel.

- - - Updated - - -

Hi,

This code could be synthesize but for simulation, how can i do???

thank you.
Jose Miguel.

 

[vipinlal]

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_counter16 is
end entity  tb_counter16;

architecture archtb_counter16 of tb_counter16 is 
signal sCLK: std_logic;
signal snRST: std_logic;
signal sQ: unsigned(7 downto 0);

begin
dut: entity work.counter16
	
	port map(sCLK,
				snRST,
				sQ);
				
	snRST <= '0' , '1' after 2 ns;
	
	sCLK <= not sCLK after 4 ns;
	
end archtb_counter16;

Use the above code also, if you want to simulate.

remember that the testbench code is used only for simulation and is not synthesisable.

 

[joseMiguel]

Hi,

How can i have with Modelsim-Altera the signals from the testbench and have the simulation working?

Thank you.
Jose Miguel

 

[raystings]

Hi,

This code could be synthesize but for simulation, how can i do???

thank you.
Jose Miguel.

- - - Updated - - -

Hi,

This code could be synthesize but for simulation, how can i do???

thank you.
Jose Miguel.

I usually use scripts for simulation. Below is a zip file with the complete sources (counter16.vhd, Testbench, etc.) The simulation will only work if you have installed Modelsim on your computer.
View attachment counter16.zip

- Unzip the file
- double click counter16\modelsim.bat

This way Modelsim should start automatically and the simulation should be shown.

Good luck!

 

[joseMiguel]

Hi,

Thank you, I succeed to run the simulation with modelsim-altera.
But i don't succeed directly from QUARTUS.


best regards
joseMiguel