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Ask about the timing in FPGA...

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TRUNGDPHAN

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Anyone has a source code which can delay 1 second using FPGA. Please give me a copy? Source code is written in MAX+PLUS II. Thanks a lot
 

cube007

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Hello TRUNGDPHAN,

There will be no source code for a delay of 1 second because it is not possible to synthesize timings. Instead you have to use a counter which counts every rising edge of a clock signal.

For example:
clk = 10 MHz --> t = 100 ns
1 secound / 100 ns = 10.000.000 (10 M)

So you will need a counter which counts from 0 to 9.999.999 or from 9.999.999 down to 0 which is more efficient because a comparator to 0 needs less space. A counter for 10 M needs 2^24 bits.

Which type of HDL do you want to use? VHDL, Verilog, AHDL? What’s your applications? What’s the input frequency?

Bye,
cube007
 

omid219

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The only solution is using a counter and a clock reference. Lower clock reference rate means smaller counter size.
 

deniza

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You must write in xHDL language sync counter or generate it with Altera's Mega Wizard.
 

ye.hui

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you should never think about using delay circuits to implement any specified delay because the delay may be variable after each place and route. the counter is a good choice.
 

echo47

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TRUNGDPHAN, what type of signal do you want to delay? If it's a simple event, then use a clocked counter as described above. If it's some sort of data, then feed the data through a long shift register (perhaps implemented in RAM), clocked at a frequency equal to the shift register length.
 

TRUNGDPHAN

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Thank you for your answers.
I use the XC2S200E Sparktan-2E chip of Xilinx. Clock signal is about 50MHz.
I don't know how to relate the system clock signal with my clock signal which I use to write my program.
Please show me to know clearly.
 

dragon_boat

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you can divide ur frequence by n num.
for example , 50M / 10 = 5 M , so it is
easy to do that by using counter.
 

TRUNGDPHAN

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Have you ever written code for the 8051 (or 89C51) microcontroller?
in 8051, if you use Xtal 12MHz, one machine cycle is 1 microsecond. the instructions in the instruction set of the 8051 microcontroller are timing based on the machine cycle. So I use a loop (or timer ) to delay (base on the number of executed instructions in the loop).
So on, I wonder that:
+ timing in FPGA is similar to the microcontroller?
+ I can delay in FPGA using system clock not my outside clock?
Please show me to understand clearly about the problems.
Thank you very much for your help.
 

floatgrass

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dragon_boat's answer is easier for u.
you can divide ur frequency with a rather large number your chip supports. then delay 1s is easy by timer.
good luck
 

echo47

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TRUNGDPHAN said:
what does ur mean?
ur = your
u = you

They are common english internet typing shortcuts.
This is an international forum. Everyone, please try to write clear sentences!
 

tkbits

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TRUNGDPHAN said:
in 8051, if you use Xtal 12MHz, one machine cycle is 1 microsecond. the instructions in the instruction set of the 8051 microcontroller are timing based on the machine cycle.

The data sheets contain instruction timing based on 1 microsecond machine cycle, but the timing diagrams for the control signals probably show timing based on the 12 MHz clock.
 

TRUNGDPHAN

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Yes, that's all right. I said that one machine cycle is 1 microsecond if we use the 12 MHz crystal. if we use a different crystal, we should look up datasheet (normally, one instruction is calculated on oscillator period = 1/f).
but in FPGA, we only have a delay time range from input to output. please make me know clearly:
+ delay in FPGA is the same as I've worked for microcontroller.
+ if it is not the same, please show me how to delay using system clock (no using ext. clock signal)
Thanks
 

sp

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i would like to add something....

for delay...im using counter to count and then compare (comparator) the desired input value of delay.... if input is 1001 n the counter is in 1001 state then it will generate signal of stating delay is enuff...

another 1 i try is to increase the state in the state machine...which for this state it does nth but just wait to go to another state when rising edge of clock....this can build up the delay when more blank state added...

is there anything wrong or weakness in above ...kindly advised me....

another question is if the clock is 1GHz,,,,,if v use counter for delay....i think the flip-flops required would b incredible,,,,,am i right,,,, any other options...

thank you...

regards,
sp
 

pstar

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You have to use a counter. You can use this module have delay:

// Divide Clock
module CNTDIV (CLK,Qout);

input CLK;
output Qout;

wire Qout;

reg [N:0] COUNT;

always @(posedge CLK) COUNT = COUNT + 1;

assign Qout = COUNT[N];

endmodule


You need to use formula N= Log2(T)+Log2(BT)-1 to find number of bits you need for counter. Replace this number whenever you have N in module.

Where T=Time and BT=Board Clock (For example 50*10^6).

I hope this can help.

:)
 

jay_ec_engg

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I use counter....
say i m asserting some signal at Xsec and de-assert that after X+1 sec so,

sig = 1;
counter = 0;
rising edge (clk)
counter = counter +1;
if (counter == ZZZ) // Desired counts for 1 Sec
sig = 0;
else
sig = 1;
end if;
end rising clokc loop
 

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