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ASIC Verification position tips and tools?

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sagar_satish

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Hi,

I just received an offer from a good company for an entry-level ASIC design verification position. The position starts in about 2 weeks and I am a new graduate and I have a few questions from people who have worked in this line before:

1) What should I be brushing up on over the next few weeks? Right now I can trying to get my C++ programming and Verilog skills up by studying and practicing on my own.

2) Any particular books that I would find handy?

3) Any general tips on how to approach the field so I can learn as much as possible and be able to contribute to team?

Thanks in advance
 

ashishk

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Apart from Verilog,try to learn some HVL as well like system verilog. Now a days most of the people use SV for verification.Since you already know C++ so you should not be having any issues with OOPs concepts of SV . For learning it you should be readinf from LRM(IEEE 1800-2009) or can refer System Verilog for Verification by Chris Spear . Once you are comfortable with SV then you can learn Verification Methodology like OVM/UVM etc .
 

ljxpjpjljx

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yes , you should know the verification methodology and flow and study SV and system C!
 

cuiya

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Learn Specman, SystemVerilog and VMM. How to architect testbenches so it is reusable, flexible and can enable fast testcase development. Know about what a BFM, Driver, Monitor, Random Generator, Scoreboard is.

Also depend on the stuff they work on you might want to read up on bus specifications. Like ethernet, front side bus, ahb, pci express...
 

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